CFP last date
20 January 2025
Call for Paper
February Edition
IJCA solicits high quality original research papers for the upcoming February edition of the journal. The last date of research paper submission is 20 January 2025

Submit your paper
Know more
The week's pick
Responsive image
SFLA-Based Line Balancing and Task Optimization in Master-Slave Controlled Hanger Transportation Systems for Garment Production

Duc Hoang Nguyen
Random Articles
Reseach Article

Dual Material Gate Nanoscale SON MOSFET: For Better Performance

Published on June 2013 by Bibhas Manna, Saheli Sarkhel, Ankush Ghosh, S. S. Singh, Subir Kumar Sarkar
journal_cover_thumbnail

International Conference on Communication, Circuits and Systems 2012
Foundation of Computer Science USA
IC3S - Number 4
June 2013
Authors: Bibhas Manna, Saheli Sarkhel, Ankush Ghosh, S. S. Singh, Subir Kumar Sarkar
39e78d07-6be6-4c03-a5db-16d5058c0247

Bibhas Manna, Saheli Sarkhel, Ankush Ghosh, S. S. Singh, Subir Kumar Sarkar . Dual Material Gate Nanoscale SON MOSFET: For Better Performance. International Conference on Communication, Circuits and Systems 2012. IC3S, 4 (June 2013), 7-9.

@article{
author = { Bibhas Manna, Saheli Sarkhel, Ankush Ghosh, S. S. Singh, Subir Kumar Sarkar },
title = { Dual Material Gate Nanoscale SON MOSFET: For Better Performance },
journal = { International Conference on Communication, Circuits and Systems 2012 },
issue_date = { June 2013 },
volume = { IC3S },
number = { 4 },
month = { June },
year = { 2013 },
issn = 0975-8887,
pages = { 7-9 },
numpages = 3,
url = { /proceedings/ic3s/number4/12304-1344/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Communication, Circuits and Systems 2012
%A Bibhas Manna
%A Saheli Sarkhel
%A Ankush Ghosh
%A S. S. Singh
%A Subir Kumar Sarkar
%T Dual Material Gate Nanoscale SON MOSFET: For Better Performance
%J International Conference on Communication, Circuits and Systems 2012
%@ 0975-8887
%V IC3S
%N 4
%P 7-9
%D 2013
%I International Journal of Computer Applications
Abstract

A simple analytical model of a nanoscale fully depleted dual- material gate (DMG) SOI and SON MOSFETs has been developed and their performance comparison analysis is presented in this paper. An analytical model for the surface potential and threshold voltage has been developed both for these structures using a generalized 2D Poisson's equation solution. The DMG SON MOSFET technology is found to have more potential against various short channel effects (SCEs) thereby offering further device scalability with improved immunity.

References
  1. The International Technology Roadmap for Semiconductor, Emerging Research Devices, 2009.
  2. COLINGE J P. Silicon on insulator technology: materials to VLSI. 2nd ed. Norwell, MA: Kluwer: Kluwer Academic Publishers; 1997.
  3. JURCZAK. M. , et al, Silicon-on-Nothing (SON)-an Innovative Process for Advanced CMOS, IEEE Transactions on Electron Devices, 2000; 47(11), 2179-2187.
  4. PRETET. J. et al. , Silicon-on-Nothing MOSFETs: Performance, Short-Channel Effects, and Backgate Coupling, IEEE Transactions on Electron Devices, 2004; 51(2), 240-246.
  5. G. Venkateshwar Reddy and M. Jagadesh Kumar, "A New Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET-Two-Dimensional Analytical Modeling and Simulation", IEEE Transactions on Electron Devices,vol. . 4, no. 2, pp. 260-268, 2005.
  6. K. Suzuki and T. Sugii, "Analytical models for n+-p+ double gate SOI MOSFET's", IEEE Transaction on . Electron Devices, vol. 42, pp. 1940-1948, 1995.
  7. Saptarsi Ghosh, Khomdram Jolson Singh, Sanjoy Deb and Subir Kumar Sarkar, "Two dimensional analytical modeling for SOI and SON MOSFET and their performance comparison", JNEP. 3(2011), No. 1, P. 569-57.
Index Terms

Computer Science
Information Sciences

Keywords

Soi/son Mosfet Threshold Voltage Short Channel Effect Dibl