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Performance Analysis of AlInN/GaN Underlap DG MOSFET for varying Underlap and Gate length
| International Conference on Communication, Circuits and Systems 2012 |
| Foundation of Computer Science USA |
| IC3S - Number 4 |
| June 2013 |
| Authors: Hemant Pardeshi, N. Mohankumar, Chandan Kumar Sarkar |
| 7dbe669b-f857-4db1-b489-64416b302d18 |
Hemant Pardeshi, N. Mohankumar, Chandan Kumar Sarkar . Performance Analysis of AlInN/GaN Underlap DG MOSFET for varying Underlap and Gate length. International Conference on Communication, Circuits and Systems 2012. IC3S, 4 (June 2013), 1-3.
Abstract
In this work, we investigate the performance of 18nm gate length AlInN/GaN Heterostructure Underlap Double Gate MOSFETs, using 2D Sentaurus TCAD simulation. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to large two-dimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of major device performance metrics such as DIBL, SS, delay, and Ion/Ioff ratio have been done for varying gate length (Lg) and underlap length (Lun). Impressive results for Delay, Ion, and DIBL are obtained. The results indicate that there is a need to optimize the Ioff and SS values for specific logic design.
References
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