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Analytical Drain Current Model for Symmetrical Gate Underlap DGMOSFET

Published on June 2013 by Sudhansu Kumar Pati, Hemant Pardeshi, Godwin Raj, Chandan Kumar Sarkar, Arghyadeep Sarkar, N Mohan Kumar
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International Conference on Communication, Circuits and Systems 2012
Foundation of Computer Science USA
IC3S - Number 3
June 2013
Authors: Sudhansu Kumar Pati, Hemant Pardeshi, Godwin Raj, Chandan Kumar Sarkar, Arghyadeep Sarkar, N Mohan Kumar
b19e1e8a-5f99-4e3a-b660-501b66a8fd1b

Sudhansu Kumar Pati, Hemant Pardeshi, Godwin Raj, Chandan Kumar Sarkar, Arghyadeep Sarkar, N Mohan Kumar . Analytical Drain Current Model for Symmetrical Gate Underlap DGMOSFET. International Conference on Communication, Circuits and Systems 2012. IC3S, 3 (June 2013), 26-28.

@article{
author = { Sudhansu Kumar Pati, Hemant Pardeshi, Godwin Raj, Chandan Kumar Sarkar, Arghyadeep Sarkar, N Mohan Kumar },
title = { Analytical Drain Current Model for Symmetrical Gate Underlap DGMOSFET },
journal = { International Conference on Communication, Circuits and Systems 2012 },
issue_date = { June 2013 },
volume = { IC3S },
number = { 3 },
month = { June },
year = { 2013 },
issn = 0975-8887,
pages = { 26-28 },
numpages = 3,
url = { /proceedings/ic3s/number3/12301-1339/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Communication, Circuits and Systems 2012
%A Sudhansu Kumar Pati
%A Hemant Pardeshi
%A Godwin Raj
%A Chandan Kumar Sarkar
%A Arghyadeep Sarkar
%A N Mohan Kumar
%T Analytical Drain Current Model for Symmetrical Gate Underlap DGMOSFET
%J International Conference on Communication, Circuits and Systems 2012
%@ 0975-8887
%V IC3S
%N 3
%P 26-28
%D 2013
%I International Journal of Computer Applications
Abstract

The drain current model of symmetrical Underlap DGMOSFET is evaluated for subthreshold region. Model data is verified with simulation data for validation of the proposed model. For validation the drain current is evaluated with respect to gate to source potential. The drain current is calculated with variation of gate length, underlap length and silicon body thickness. As the gate length and underlap length increases, the drain current decreases and as silicon body thickness increases, increase of drain current is observed.

References
  1. Kranti, T. , M. Chung, and J. -P. Raskin, "Analysis of static and dynamic performance of short channel double gate SOI MOSFETs for improved cut-off frequency," Jpn. J. Appl. Phys. , vol. 44, no. 4B, 2005, pp. 2340- 2346.
  2. D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H. -S. P. Wong, "Device scaling limits of Si MOSFETs and their application dependencies,"Proc. IEEE, vol. 89, Mar. 2001, pp. 259–288.
  3. J. G. Fossum, M. M. Chowdhury, V. P. Trivedi, T. J. King, Y. K. Choi, J. An, and B. Yu, "Physical insights on design and modeling of nanoscale FinFETs," inIEDM Tech. Dig. , 2003, pp. 29. 1. 1–29. 1. 4.
  4. V. Trivedi, J. G. Fossum, and M. M. Chowdhury, "Nanoscale FinFETs with gate-source/drain underlap," IEEE Trans. Electron Devices, vol. 52, no. 1, Jan. 2005, pp. 56–62. V.
  5. H. Soeleman, K. Roy, and B. C. Paul, "Robust sub-threshold logic for ultra-low power operation,"IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 9, no. 1,Feb. 2001, pp. 90–99.
  6. R. Vaddi, R. P. Agarwal, and S. Dasgupta, "Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied–independent gate and symmetric–asymmetric options," Microelectronics Journal, vol. 42, no. 5, May 2011, pp. 798-807.
  7. Kranti and G. A. Armstrong, "High Tolerance to Gate Misalignment in Low Voltage Gate-Underlap Double Gate MOSFETs," vol. 29, no. 5, 2008, pp. 503-505.
  8. Bansal, S. Member, and K. Roy, "Analytical Subthreshold Potential Distribution Model for Gate Underlap Double-Gate MOS Transistors," vol. 54, no. 7, 2007, pp. 1793-1798.
Index Terms

Computer Science
Information Sciences

Keywords

Drain Current Ultrathin Body Virtual Source Underlap Dgmosfet