International Conference on Computing, Communication and Sensor Network |
Foundation of Computer Science USA |
CCSN2014 - Number 1 |
June 2015 |
Authors: Suraj Kumar Saw, Sdk Verma, Bharat Gupta, Vijay Nath |
547d282c-b2ab-41a5-a513-b6f4d352d108 |
Suraj Kumar Saw, Sdk Verma, Bharat Gupta, Vijay Nath . An Ultra Low Power Fast Locking CMOS Phase Locked Loop for Wireless Communication. International Conference on Computing, Communication and Sensor Network. CCSN2014, 1 (June 2015), 32-36.
In this paper fast locking CMOS phase locked loop is proposed. It is designed using Cadence virtuoso gpdk 45nm CMOS technology. It is used 1 volt power supply for operation of the circuit. This proposed circuit will be very useful in clock generation in microprocessor, frequency synthesizer for cell phone, fast locking in digital aid circuits.