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Reseach Article

A Cost Effective Built-in-Self Test for Second Order Sigma Delta Modulator

Published on May 2015 by Ritika Upadhyay, Anil Kumar Sahu
National Conference Potential Research Avenues and Future Opportunities in Electrical and Instrumentation Engineering
Foundation of Computer Science USA
ACEWRM2015 - Number 3
May 2015
Authors: Ritika Upadhyay, Anil Kumar Sahu
2917ce89-e59d-484f-9e95-9f86d4ed2aa7

Ritika Upadhyay, Anil Kumar Sahu . A Cost Effective Built-in-Self Test for Second Order Sigma Delta Modulator. National Conference Potential Research Avenues and Future Opportunities in Electrical and Instrumentation Engineering. ACEWRM2015, 3 (May 2015), 29-33.

@article{
author = { Ritika Upadhyay, Anil Kumar Sahu },
title = { A Cost Effective Built-in-Self Test for Second Order Sigma Delta Modulator },
journal = { National Conference Potential Research Avenues and Future Opportunities in Electrical and Instrumentation Engineering },
issue_date = { May 2015 },
volume = { ACEWRM2015 },
number = { 3 },
month = { May },
year = { 2015 },
issn = 0975-8887,
pages = { 29-33 },
numpages = 5,
url = { /proceedings/acewrm2015/number3/20915-6047/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 National Conference Potential Research Avenues and Future Opportunities in Electrical and Instrumentation Engineering
%A Ritika Upadhyay
%A Anil Kumar Sahu
%T A Cost Effective Built-in-Self Test for Second Order Sigma Delta Modulator
%J National Conference Potential Research Avenues and Future Opportunities in Electrical and Instrumentation Engineering
%@ 0975-8887
%V ACEWRM2015
%N 3
%P 29-33
%D 2015
%I International Journal of Computer Applications
Abstract

Testing of high resolution second order sigma delta (??) modulator is a very expensive process. With the advanced technology, where the complexity over a small area is increasing, then testing at low cost with good accuracy is becoming a tedious issue for the manufacturing process. The cost effectiveness can be calculated on the basis of different parameters of the ?? modulator such as SNDR, ENOB, Gain, Offset, THD, SNR etc. Testing time also play an important role in the cost effectiveness of the modulator. The Built-in-self-test (BIST) allows the machine or circuit to test itself. BIST is desirable for the VLSI system in order to reduce the cost per chip of production –time testing by the manufacture, it can also provide the means to perform in-the field diagnostic. Therefore, this paper will demonstrate a possibility to simplify modeling and simulation of testing strategy of high-resolution ?? modulator using MATLAB SIMULINK environment. Here, we are finding the cost effectiveness on the basis of Signal to Noise Distortion Ratio (SNDR) for the ?? modulator BIST. A ?? modulation based signal generator is considered which can produce analog sinusoidal test stimuli and digital reference signal on chip. By comparing the ADC output with that of the generator reference signal, the parameter can be determined on chip based on the standard equations in the proposed simulation environment.

References
  1. Jaydip. H. Chaudhari, Gireeja D. Amin Design and Simulation of 1-bit Sigma Delta ADC in 0. 18um CMOS Technology International Journal of Computer Applications & Information Technology Vol. II, Issue I, January 2013
  2. Kook, Sehun, Aritra Banerjee, and Abhijit Chatterjee. "Dynamic Specification Testing and Diagnosis of High-Precision Sigma-Delta ADCs. " IEEE Design & Test 30. 4 (2013): 36-48.
  3. Mingyuan Ren, Tong Wu, Changchun Dong, Linghai Cui. The Design of High Performance, High Resolution Two-Order Delta-Sigma Modulator. Sensors &Transducers,Vol. 22,Special Issue, June 2013, pp. 155-162.
  4. Hsin-Wen Ting "An Output Response Analyzer Circuit for ADC Built-in Self-Test. " Springer Science+Business Media, J Electron Test Vol. 27,pp. 455–464,2011.
  5. Trivedi Preeti , Verma Ajay " Simulation of Second order Sigma Delta ADC for improving SNR upto 97dB for Software Defined Radio for 3G & 4G mobile receivers"
  6. Eloued, Sonia, Ahmed Fakhfakh, and Nabil Chouba. "High Level Modeling of a ?? Modulator for the Test of a SNDR BIST. " Systems, Signals and Devices, 2009. SSD'09. 6th International Multi-Conference on. IEEE, 2009.
  7. Hung, Shao-Feng, Hao-Chiao Hong, and Sheng-Chuan Liang. "A Low-Cost Output Response Analyzer for the Built-in-Self-Test ?-? Modulator Based on the Controlled Sine Wave Fitting Method. " Asian Test Symposium, 2009. ATS'09. . IEEE, 2009.
  8. Shaoyu U. K, Yan Han, You Cai A 3. 3V 18 Bit Digital Audio Sigma- Delta ADC in 0. 18 um CMOS Process 2007
  9. Rolindez, Luis, et al. "A SNDR BIST for/spl Sigma//spl Delta/analogue-to-digital converters. " VLSI Test Symposium, 2006. Proceedings. 24th IEEE. IEEE, 2006.
  10. Hao-Chiao Hong and Sheng-Chuan Liang "A cost effective output response analyzer for Sigma-Delta modulation based BIST systems. " (2006).
  11. Toner, Michael F. , and Gordon W. Roberts. "A BIST Scheme for an SNR Test of a Sigma-Delta ADC. " Test Conference, 1993. Proceedings. , International. IEEE, 1993.
  12. Prateek Verma, Anil Kumar Sahu ,Dr. Vivek Kumar Chandra, Dr. G. R. Sinha. A Graphical User Interface Implementation of Second Order Sigma- Delta Analog to Digital Converter with Improved Performance Parameters, INTERNATIONAL JOURNA L FOR RES EARCH IN APPLIED SCIENCE AND ENGINEERING TECHNOLO GY (I JRAS ET) Vol. 2 Issue VII, July 2014
Index Terms

Computer Science
Information Sciences

Keywords

Sigma Delta Modulator Built-in-self-test Sigma Delta Adc