The week's pick
Reseach Article
Energy Saving using Data Encoding Scheme In Network-on-Chip for LDPC Application
| National Conference on Advances in Computing, Communication and Networking |
| Foundation of Computer Science USA |
| ACCNET2016 - Number 5 |
| June 2016 |
| Authors: Pooja Painully, Kavita Joshi, Munmun Ghosal |
| e28f9e46-d40a-428a-ba1e-027273fa2e24 |
Pooja Painully, Kavita Joshi, Munmun Ghosal . Energy Saving using Data Encoding Scheme In Network-on-Chip for LDPC Application. National Conference on Advances in Computing, Communication and Networking. ACCNET2016, 5 (June 2016), 9-13.
Abstract
Communication subsystems such as routers and wired or wireless network interfaces consume more power in network on chip. With the target of reduction in power consumption in network on chip, three encoding schemes are presented in this paper. These schemes work at flit level which results in reduction of self and coupling transition without making modification in the link architecture and routers. Globally to defend memories from soft error correction codes have been used which make changes in logical value of memory cubicles without destructing the circuit. As memory expands, demand of complex decoder rises due to complex codes. One of such decoder is LDPC. We can apply these encoding schemes to linear density parity check (LDPC) codes. Power dissipation is reduced. The dynamic power value reduction is verified by using x-power analyzer tool.
References
- W. Wolf, A. A. Jerraya, and G. Martin, "Multiprocessor system-on-chipMPSoC technology," IEEE Trans. Comput. -Aided Design Integr. CircuitsSyst. , vol. 27, no. 10, pp. 1701–1713, Oct. 2008.
- A. Vittal and M. Marek-Sadowska, "Crosstalk reduction for VLSI,"IEEE Trans. Comput. -Aided Design Integr. Circuits Syst. , vol. 16, no. 3,pp. 290–298, Mar. 1997.
- L. Benini and G. De Micheli, "Networks on chips: A new SoCparadigm," Computer, vol. 35, no. 1, pp. 70–78, Jan. 2002.
- S. E. Lee and N. Bagherzadeh, "A variable frequency link for apowerawarenetwork-on-chip (NoC)," Integr. VLSI J. , vol. 42, no. 4,pp. 479–485, Sep. 2009.
- K. Banerjee and A. Mehrotra, "A power-optimal repeater insertion methodology for global interconnects in nanometer designs",IEEE Trans. Electron Devices, vol. 49, no. 11, pp. 2001–2007, Nov. 2002.
- C. Seiculescu, S. Murali, L. Benini, and G. De Micheli, "SunFloor 3D: A tool for networks on chip topology synthesis for 3-D systems on chips," in Proc. IEEE Trans. Comput. -Aided Design Integr. Circuits Syst. , vol. 29, no. 12, pp. 1987–2000, Dec. 2010.
- M. Palesi, R. Tornero, J. M. Orduñna, V. Catania, and D. Panno,"Designing robust routing algorithms and mapping cores in networks-onchip: A multi-objective evolutionary-based approach," J. Univ. Comput Sci. , vol. 18, no. 7, pp. 937–969, 2012.
- S. Youngsoo, C. Soo-Ik, and C. Kiyoung, "Partial bus-invert coding for power optimization of application-specific systems," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 9, no. 2, pp. 377–383, Apr. 2001.
- Paul Wettin, Ryan Kim, Jacob Murray, Xinmin Yu, Partha P. Pande, Amlan Ganguly, Deukhyoun Heo, "Design Space Exploration for Wireless NoCs Incorporating Irregular Network Routing", IEEE Trans. on computer-aided design of integrated circuits and system, VOL. 33, NO. 11, Nov. 2014
Index Terms
Keywords