In earlier generation of IC design technologies the prime parameters of concern were timing and silicon area. The increasing demand for high-performance, battery-operated, system-on-chips in communication and computing has shifted the focus from traditional constraints (such as area, performance, cost, and reliability) to power consumption [1]. In recent years device densities and clock frequency have increased dramatically in devices thereby increasing the power consumption dramatically. During design process the most critical power requirements are tested only after power pins becomes explicit. There are different design strategies for reducing power consumption, and it also becomes critical to make power aware design even if power pins were not explicit or say at very abstraction level of design flow. UPF is used as an IEEE 1801 standard method which provides a consistent way to specifying power implementation intent throughout the design process [2]. Low power validation at very abstraction level uses RTL/Behavioral HDL model along with UPF intent. UPF provide an ability to verify the power intent behavior as early as possible or say at higher abstraction level by overlay the power behavior over the RTL/Behavior HDL model at same abstraction level. This paper describes how HDL model impacted at very higher abstraction level to meet certain power constraints and their validation using an industry accepted IEEE 1801 standard UPF low power validation flow.

HDL (Hardware Description Language) RTL (Register Transfer Level) UPF (Unified Power Format) EDA (Electronic Design Automation) CAD (Computer Aided Design) TCL (Tool Command Language).