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Power and Area Efficient FLASH ADC Design using 65nm CMOS Technology

by M. Abhilash Kumar, Ajay Kumar Dadoria, Kavita Khare
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 97 - Number 23
Year of Publication: 2014
Authors: M. Abhilash Kumar, Ajay Kumar Dadoria, Kavita Khare
10.5120/17319-7431

M. Abhilash Kumar, Ajay Kumar Dadoria, Kavita Khare . Power and Area Efficient FLASH ADC Design using 65nm CMOS Technology. International Journal of Computer Applications. 97, 23 ( July 2014), 1-8. DOI=10.5120/17319-7431

@article{ 10.5120/17319-7431,
author = { M. Abhilash Kumar, Ajay Kumar Dadoria, Kavita Khare },
title = { Power and Area Efficient FLASH ADC Design using 65nm CMOS Technology },
journal = { International Journal of Computer Applications },
issue_date = { July 2014 },
volume = { 97 },
number = { 23 },
month = { July },
year = { 2014 },
issn = { 0975-8887 },
pages = { 1-8 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume97/number23/17319-7431/ },
doi = { 10.5120/17319-7431 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:24:52.259131+05:30
%A M. Abhilash Kumar
%A Ajay Kumar Dadoria
%A Kavita Khare
%T Power and Area Efficient FLASH ADC Design using 65nm CMOS Technology
%J International Journal of Computer Applications
%@ 0975-8887
%V 97
%N 23
%P 1-8
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper presents a design of a high speed Comparator design using 65nm digital CMOS technology on Cadence Virtuoso Design Tool. The proposed FLASH ADC Design consists of fully differential topology. The first stage provides a Voltage Divider circuit and the second stage is Comparator Design having high sampling frequency tolerance, and the high efficient common drain circuit provides high driving capability with relatively low power dissipation. It is used in more application for bandwidth and power and a high resolution is available for analog-to-digital converters (ADCs). Under 1 V supply voltage, the simulation results show that the proposed FLASH ADC Design is having a differential topology along with latching circuit.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Analog to Digital convertor(ADC) common mode feedback (CMFB) circuits Complementary metal oxide semiconductor (CMOS) Voltage full scale range(VFSR) Differential non linearity (DNL) Least significant bit (LSB) Most significant bit (MSB) TSPCR(True Single-Phase Clock register).

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