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Reseach Article

Parametric Fault Detection of Analogue Circuits

by Sherif Anis, Mohamed H. El-mahlawy, Mahmoud E. A. Gadallah, Emad A. El-samahy
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 96 - Number 9
Year of Publication: 2014
Authors: Sherif Anis, Mohamed H. El-mahlawy, Mahmoud E. A. Gadallah, Emad A. El-samahy
10.5120/16821-6575

Sherif Anis, Mohamed H. El-mahlawy, Mahmoud E. A. Gadallah, Emad A. El-samahy . Parametric Fault Detection of Analogue Circuits. International Journal of Computer Applications. 96, 9 ( June 2014), 14-23. DOI=10.5120/16821-6575

@article{ 10.5120/16821-6575,
author = { Sherif Anis, Mohamed H. El-mahlawy, Mahmoud E. A. Gadallah, Emad A. El-samahy },
title = { Parametric Fault Detection of Analogue Circuits },
journal = { International Journal of Computer Applications },
issue_date = { June 2014 },
volume = { 96 },
number = { 9 },
month = { June },
year = { 2014 },
issn = { 0975-8887 },
pages = { 14-23 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume96/number9/16821-6575/ },
doi = { 10.5120/16821-6575 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:21:17.122143+05:30
%A Sherif Anis
%A Mohamed H. El-mahlawy
%A Mahmoud E. A. Gadallah
%A Emad A. El-samahy
%T Parametric Fault Detection of Analogue Circuits
%J International Journal of Computer Applications
%@ 0975-8887
%V 96
%N 9
%P 14-23
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper presents a new testing approach for analogue circuits based on the digital signature analysis. In this paper, the efficient parametric fault detection approach for analogue circuits using the simulation environment is presented. This approach has three main parts, an analogue test pattern generator (ATPG), an analogue test response compactor (ATRC), and an analogue circuit under test (ACUT) model, build in the PSpice circuit simulator. The proper ATPG is designed to sweep the applying sinusoidal frequencies to match the frequency domain of the ACUT. The output test response of the ACUT is acquired via the analogue-to-digital converter (ADC). The ATRC accumulates digital samples of the output response from the ADC to generate a digital signature that can characterize the situation of the ACUT. The signature comparison is achieved based on signature boundaries based on the worst-case analysis. In addition, the signature curve for each component variations of the ACUT is presented to be illustrated as image of some parameters affected in the transfer function of the ACUT. It combines effective parameters of the transfer function of the ACUT with respect to the component variations. These parameters are the band-with and the passband transmission. Using the signature curve, a parametric fault of each component of the ACUT can be detected under the sweep sinusoidal frequency of the ATPG. The presented testing approach is applied to the analogue benchmark circuit to validate the presented testing approach.

References
  1. Mohamed H. El-Mahlawy, E. A. El-Sehely, A. S. Ragab, and S. Anas, "Design and Implementation of a New Built-In Self-Test Boundary Scan Architecture," Proceedings of the IEEE 15th International conference on Microelectronics, pp. 27-31, Cairo, Egypt, 2003.
  2. Mohamed H. El-Mahlawy, S. Anas, E. A. El-Sehely, and A. S. Ragab, "New Automatic Testing Architecture For Integrated Circuits," Proceedings of the 5th International Conference of the Electrical Engineering (ICEENG), Military Technical College, Cairo, Egypt, 2006.
  3. Mohamed H. El-Mahlawy and A. Seddik, "Design and Implementation of New Automatic Testing System for Digital Circuits Based on the Signature Analysis," Proceedings of the 12th International Conference on Aerospace Sciences & Aviation Technology (ASAT), Military Technical College, Cairo, Egypt, 2007.
  4. Mohamed H. El-Mahlawy and E. H. Khalil, "A New Delay Built-In Self-Test Architecture Using Boundary Scan in Synchronous Mode," Proceedings of the 12th International Conference on Aerospace Sciences & Aviation Technology (ASAT), pp. 29-31, Military Technical College, Cairo, Egypt, 2007.
  5. Mohamed H. El-Mahlawy, A. Abd El-Wahab, and A. S. Ragab, "FPGA Implementation of The Portable Automatic Testing System for Digital Circuits," Proceedings of the 6th International Conference of the Electrical Engineering (ICEENG), Military Technical College, Cairo, Egypt, 2008.
  6. Mihalis Psarakis, Dimitris Gizopoulos, Ernesto Sanchez and Matteo S. Reorda, "Microprocessor Software-Based Self-Testing", IEEE Design & Test of Computers, pp. 4-18, May/June, 2010.
  7. Sherif I. Morsy, Mohamed H. El-Mahlawy, Gouda I. Mohamed, "Hybrid based Self-Test Solution for Embedded System on Chip", International Journal of Computer Applications, Volume 84, No 12, December 2013.
  8. M. A. Mousa, "Digital Testing of Analogue Systems,", Ph. D. thesis, Department of Electronic and Electrical Engineering, University of Strathclyde, Glasgow, United Kingdom, October, 2002.
  9. Z. Guo, J. Savir, "Analog Circuit Test using Transfer Function Coefficient Estimates," International Test Conference, pp. 1155 - 1163, 2003.
  10. Milor, L. S. "A tutorial introduction to research on analogue and mixed-signal circuit testing," IEEE Transactions Circuits and Systems-II: Analogue and Digital Signal Processing, vol. 45, pp. 1389-1407, 1998.
  11. Taylor, D. , "Transient response testing of analogue components in mixed-signal systems: a review," IEE Proc. Circuits, Devices and Systems, vol. 145, pp. 314-318, 1998.
  12. Towill, D. R. : "The engineering of impulse response testing using pseudo-noise stimuli," Proc. of IEEE Autotestcon, pp. 225-232, 1977.
  13. Robson, M. and Russell, G. : "Digital techniques for testing analogue functions," Proc. of IEE Colloquium 'Systems Design for Testability', Digest No. 1995/083, pp. 6/1-4, 1995.
  14. A. Singh, C Patel, J. Plusquellic, "On-Chip Impulse Response Generation for Analog and Mixed-Signal Testing," proceeding of International Test Conference (ITC), 2004.
  15. Souders, T. M. and Flach, D. R. : "Accurate frequency response determinations from discrete step response data," IEEE Transaction on Instrumentation and Measurement, vol. IM-36, pp. 433-9, 1987.
  16. Chin, K. R. : "Functional testing of circuits and SMD boards with limited nodal access," Proc. of International Test Conference, pp. 129-43, 1989.
  17. John G. Webster, "Medical Instrumentation Application and Design," Third Edition, Wiley and Sons Inc. , 1998.
  18. Pan, C. Y. and Cheng, K. T. : "Pseudorandom testing for mixed-signal circuits," IEEE Transactions Computer-Aided Design of Integrated Circuits and Systems, vol. 18, pp. 1173-1185, 1997.
  19. Variyam, P. N. , Chatterjee, A. : "Digital-compatible BIST for analog circuits using transient response sampling," IEEE Design & Test of Computers, pp. 106-115, 2000.
  20. Bekheit, M. A. M. , Hamilton, D. J. and Stimpson, B. P. : "Testing analogue circuits with binary sequences: a feasibility study", Proc. of International Mixed-Signal Test Workshop, Montreux-Switzerland, 18-21 June 2002.
  21. Sunil R. Das, Jila Zakizadeh, Satyendra Biswas, Mansour H. Assaf, Amiya R. Nayak, Emil M. Petriu, Wen-Ben Jone, and Mehmet Sahinoglu, "Testing Analog and Mixed-Signal Circuits With Built-In Hardware — A New Approach," IEEE Transactions on Instrumentation and Measurement, vol. 56, NO. 3, June 2007.
  22. B. K. S. V. L. Varaprasad, Lalit Mohan Patnaik, Hirisave S. Jamadagni, and V. K. Agrawal, "A New ATPG Technique (MultiDetect) for Testing of Analog Macros in Mixed-Signal Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, NO. 2, Feb. 2004.
  23. Jeongjin Roh and Jacob A. Abraham,"Subband Filtering for Time and Frequency Analysis of Mixed-Signal Circuit Testing," IEEE Transactions on Instrumentation and Measurement, vol. 53, NO. 2, APRIL 2004.
  24. MicroSim Corporation, "MicroSim Application Notes," Version 8. 0, June, 1997.
  25. Mohamed. H. El-Mahlawy, "A Novel Testing Method for Monostable Multivibrators," Proceedings of the 5th International Conference of the Electrical Engineering (ICEENG), Military Technical College, Cairo, Egypt, 2006.
  26. R. Kondagunturi, E. Bradley, K. Maggard, C. Stroud, "Benchmark Circuits for Analog and Mixed-Signal Testing," Proceeding of the IEEE Southeast Regional Conference, pp. 217-220, 1999.
Index Terms

Computer Science
Information Sciences

Keywords

Fault detection Parametric faults Signature analysis of analogue testing Testing of analogue circuits.