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True Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique

by Priyanka Sharma, Rajesh Mehra
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 96 - Number 11
Year of Publication: 2014
Authors: Priyanka Sharma, Rajesh Mehra
10.5120/16842-6698

Priyanka Sharma, Rajesh Mehra . True Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique. International Journal of Computer Applications. 96, 11 ( June 2014), 44-51. DOI=10.5120/16842-6698

@article{ 10.5120/16842-6698,
author = { Priyanka Sharma, Rajesh Mehra },
title = { True Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique },
journal = { International Journal of Computer Applications },
issue_date = { June 2014 },
volume = { 96 },
number = { 11 },
month = { June },
year = { 2014 },
issn = { 0975-8887 },
pages = { 44-51 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume96/number11/16842-6698/ },
doi = { 10.5120/16842-6698 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:21:31.586192+05:30
%A Priyanka Sharma
%A Rajesh Mehra
%T True Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique
%J International Journal of Computer Applications
%@ 0975-8887
%V 96
%N 11
%P 44-51
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper enumerates the design of low power and high speed double edge triggered True Single Phase Clocking (TSPC) D- flip-flop. The TSPC CMOS flip-flop uses only one clock signal that is never inverted and it eliminates the clock skew. The originally developed TSPC flip-flop are very sensitive to the clock slope and large portion of power is spent in pre-charging the internal nodes, which makes TSPC dynamic circuits less power efficient. In the conventional CMOS design, high leakage current is becoming a significant contributor to power dissipation. To overcome the existing problem of CMOS TSPC D flip-flop, a Multi-threshold CMOS (MTCMOS) technology is used for leakage minimization. The designed flip-flops are compared in terms of power consumption and propagation delay and power delay product and simulations are carried out by MICROWIND 3. 1 tools. The proposed MTCMOS designs such as original MTCMOS implmentation and NMOS insertion in MTCMOS design of TSPC D flip-flop saves static power 57. 517% and 58. 871% as compared to conventional DE-TSPC D flip-flop respectively at 1. 2V.

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Index Terms

Computer Science
Information Sciences

Keywords

DE-TSPC flip-flop MTCMOS power dissipation figure of merit (FOM) BSIM.

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