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Reseach Article
High-Resolution CMOS Counter Type ADC Layout Design by using Transmission Gate Logic
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 95 - Number 23 |
| Year of Publication: 2014 |
| Authors: Lucky Prajapati, Teena Raikwar, Puran Gour |
10.5120/16731-5665
|
Lucky Prajapati, Teena Raikwar, Puran Gour . High-Resolution CMOS Counter Type ADC Layout Design by using Transmission Gate Logic. International Journal of Computer Applications. 95, 23 ( June 2014), 1-3. DOI=10.5120/16731-5665
Abstract
In this paper, we propose counter type ADC for high-speed applications. Counter type ADCs are one of the most popular ADC topology used to implement moderate resolution converter due to their reasonably fast conversion time and simplicity. . Designed ADC has 8 input channels each of which has 0 – 2. 6 V signal range. The resolution of ADC the converter is 8 bits. The amount of passing through a system from input to output ADCs can be increased by using its technique This is implemention on the circuit level with pass transistor circuit. The primary focus of this work design and implementation of a pass transistor based Analog-to-Digital converter. The proposed counter type ADC is composed of a 8-bit DAC design by using transmission gate logic, a comparator logic , 8 bit digital counter and "AND" gates to pass the clock signal by considering the chip area, operation speed, and circuit complexity.
References
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