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Performance Analysis of Various Fragmentation Techniques in Runtime Partially Reconfigurable FPGA
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 94 - Number 8 |
| Year of Publication: 2014 |
| Authors: Senoj Joseph, K. Baskaran |
10.5120/16367-5783
|
Senoj Joseph, K. Baskaran . Performance Analysis of Various Fragmentation Techniques in Runtime Partially Reconfigurable FPGA. International Journal of Computer Applications. 94, 8 ( May 2014), 39-43. DOI=10.5120/16367-5783
Abstract
Reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), are very popular in today's embedded systems design due to their low-cost, high-performance and flexibility. Partially Runtime-Reconfigurable (PRTR) FPGAs allow hardware tasks to be placed and removed dynamically at runtime. A novel 2D area fragmentation metric that takes into account feasibility of placement of future task arrivals is presented. Simulation experiments indicate that proposed technique yield better results than existing fragmentation estimation techniques when used in fragmentation aware placement.
References
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