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An Algorithm for Leakage Power Reduction through IVC in CMOS VLSI Digital Circuits
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 94 - Number 7 |
| Year of Publication: 2014 |
| Authors: Manikya Vara Prasad Done, Uday Panwar, Kavita Khare |
10.5120/16356-5740
|
Manikya Vara Prasad Done, Uday Panwar, Kavita Khare . An Algorithm for Leakage Power Reduction through IVC in CMOS VLSI Digital Circuits. International Journal of Computer Applications. 94, 7 ( May 2014), 24-28. DOI=10.5120/16356-5740
Abstract
Leakage current in CMOS circuits can be controlled at the circuit level and at the device level as well. One of the circuit level control techniques is the Input Vector Control (IVC). By using IVC, leakage power consumption of a circuit can be reduced in the sleep state. In this paper, an algorithm has been given to determine the optimum input vector that can be applied to the circuit in the sleep state for getting low leakage power. This algorithm uses the concept of controllability of the nodes in the circuit and the dependency of a gate on the remaining gates in the circuit to determine the optimum input vector. The proposed algorithm has been applied on an ISCAS benchmark circuit C17, the results showed that the algorithm gives a vector having a leakage nearer to the vector obtained using exhaustive search in CADENCE that gives low leakage value with less execution time as well.
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