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Low Power Magnitude Comparator Circuit Design
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 94 - Number 1 |
| Year of Publication: 2014 |
| Authors: Vijaya Shekhawat, Tripti Sharma, K. G. Sharma |
10.5120/16308-5535
|
Vijaya Shekhawat, Tripti Sharma, K. G. Sharma . Low Power Magnitude Comparator Circuit Design. International Journal of Computer Applications. 94, 1 ( May 2014), 22-24. DOI=10.5120/16308-5535
Abstract
This paper presents a new low power 2-Bit magnitude comparator using full adder technique. The proposed magnitude comparator (PTL logic) has been compared with existing magnitude comparator (GDI technique). The performance analysis of both magnitude comparators is done on basis of power consumption with respect to input voltage, temperature, and frequency; using Tanner EDA tool version 12. 6 at 45nm technology. The simulation results of proposed magnitude have shown remarkable performance in terms of power consumption, area and threshold loss in comparison to existing magnitude comparator. Thus proposed magnitude comparator can be viable option for low power application.
References
- C. -C. Wang, C. -F. Wu and K. -C. Tsai, "1-GHz 64-b high-speed comparator using ANT dynamic logic with two-phase clocking," Proc. Inst. Elect. Eng. Comput. Digital Techn, vol. 145, no. 6, pp. 433-436, Nov. 1998.
- Chung-Hsun Huang and Jinn-Shyan Wang, "High-performance and power-efficient CMOS comparator", IEEE J. Solid-State Circuits, vol. 38, pp. 254-262, Feb. 2003
- J. -S. Wang and C. -S. Huang, "High-speed and low-power CMOS priority encoder," IEEE J. Solid-State Circuits, vol. 35, pp. 1511-1514, Oct. 2000
- H. -. M. Lam and C. -Y. Tsui, "A MUX-based high-performance single-cycle CMOS comparator," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 7, pp. 591-595, Jul. 2007.
- J. -Y. Kim and H. -J. Yoo, "Bitwise competition logic for compact digital comparator," IEEE Asian Solid-State Circuit Conf. , 2007, pp. 59-62.
- N. Weste and D. Harris, CMOS VLSI Design: A Circuits and System Perspective, 3rd ed. Reading, MA, USA: Addison-Wesley May 2004.
- IEEE Transactions on Very Large Scale Intergration (VLSI) System, Vol. 10, No. 5, October, 2002.
- J. P Uyemura, Circuit Design for CMOS VLSI Norwell, MA: Khuver Academic, 1992, pp. 88-129.
- Anjuli and Satyajit Anand , "2- Bit Magnitude Comparator design using different logic styles," International Journal of Engineering Science Invention, ISSN(online):2319-6734, ISSN(Print):2319-672, Volume 2 Issue , January 2013: pp. 13-24.
- Vandana Choudhary and Rajesh Mehra, "2-Bit Comparator Using different Logic Style of full adder," International Jornal of Soft Computing and Engineering, Vol. 3, May 2013, pp. 277-279.
- Arkadiy Morgenshtein, Idan Shwartz and Alexander Fish, "Gate Diffusion Input (GDI) Logic in Standard CMOS Nanoscale Process," IEEE 26-th Convention of Electrical and Electronics Engineers in Israel 2010, pp. 776-780.
- Kunal and Nidhi Kedia , "GDI Technique : A Power-Efficient Method for Digital Circuit," International Journal of Advanced Electrical and Electronic Engineering (IJAEEE), ISSN(Print):2278-8948, Volume-I, Issue-3,2012, pp. 87-93.
- N. Weste, K. Eshranghian, "Principles of CMOS Digital Design", Addision- Wesly, pp. 304-307.
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