The week's pick
Reseach Article
Low Power-High Speed 11T Full Adder DSM Design
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 93 - Number 6 |
| Year of Publication: 2014 |
| Authors: Ajay Kumar Dadoria, Kavita Khare, R. P. Singh |
10.5120/16216-5660
|
Ajay Kumar Dadoria, Kavita Khare, R. P. Singh . Low Power-High Speed 11T Full Adder DSM Design. International Journal of Computer Applications. 93, 6 ( May 2014), 1-4. DOI=10.5120/16216-5660
Abstract
Low power designs has become one of the primary focus in Deep Sub-Micron (DSM) Technology. Optimization of speed, power and area can be achieved by using Gated Diffusion Input (GDI) technique. In this paper an 11T Adder using GDI technique is proposed and it is compared with various existing adder circuits for Average Power dissipation, delay & PDP. Proposed circuit is designed using Cadence Virtuoso Tool for 180nm CMOS technology. Area has been evaluated by Microwind using TSMC BSIM 180nm technology. A comprehensive study and analysis of various Adder circuits has been done in this paper and comparison of proposed 11T adder (input 1 bit) with these circuits shows reduction in Average Power by 93. 25%, 59. 16%, 64. 09%, and 85. 28 % with respect to 28T, GDI, SERF & 8T circuits respectively. Proposed adder with 8 & 16 bit inputs are also implemented.
References
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