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Design of a Specific Instructions Set Processor for AES Algorithm

by Karim Shahbazi, Mohammad Eshghi
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 93 - Number 4
Year of Publication: 2014
Authors: Karim Shahbazi, Mohammad Eshghi
10.5120/16205-5496

Karim Shahbazi, Mohammad Eshghi . Design of a Specific Instructions Set Processor for AES Algorithm. International Journal of Computer Applications. 93, 4 ( May 2014), 36-40. DOI=10.5120/16205-5496

@article{ 10.5120/16205-5496,
author = { Karim Shahbazi, Mohammad Eshghi },
title = { Design of a Specific Instructions Set Processor for AES Algorithm },
journal = { International Journal of Computer Applications },
issue_date = { May 2014 },
volume = { 93 },
number = { 4 },
month = { May },
year = { 2014 },
issn = { 0975-8887 },
pages = { 36-40 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume93/number4/16205-5496/ },
doi = { 10.5120/16205-5496 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:14:58.542122+05:30
%A Karim Shahbazi
%A Mohammad Eshghi
%T Design of a Specific Instructions Set Processor for AES Algorithm
%J International Journal of Computer Applications
%@ 0975-8887
%V 93
%N 4
%P 36-40
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper, a new architecture for Advanced Encryption Standard (AES) Algorithm based on Application Specific Instruction set Processors (ASIP) design technique is proposed. The basic configuration is developed in order to reduce the execution clock pulses for the main specific instructions. According to the improvement of the first register configuration, two ASIPs are designed for AES algorithm. The second ASIP is 89% faster and have 22% less gates than the first proposed design.

References
  1. P. FIPS, "197," Advanced Encryption Standard (AES), vol. 26, 2001.
  2. F. Hossain, M. Ali, M. Al Abedin Syed, "A very low power and high throughput AES processor," in Computer and Information Technology (ICCIT), 2011 14th International Conference on, 2011, pp. 339-343.
  3. M. -H. Jing, Z. -H. Chen, J. -H. Chen, Y. -H. Chen, , "Reconfigurable system for high-speed and diversified AES using FPGA," Microprocessors and Microsystems, vol. 31, pp. 94-102, 2007.
  4. A. Hodjat and I. Verbauwhede, "Minimum area cost for a 30 to 70 Gbits/s AES processor," in VLSI, 2004. Proceedings. IEEE Computer society Annual Symposium on, 2004, pp. 83-88.
  5. H. Yin, H. Debiao, K. Yong, F. Xiande, "High-speed ASIC implementation of AES supporting 128/192/256 bits," in Test and Measurement, 2009. ICTM'09. International Conference on, 2009, pp. 95-98.
  6. J. M. Granado-Criado, M. A. Vega-Rodríguez, J. M. Sánchez-Pérez, J. A. Gómez-Pulido, "A new methodology to implement the AES algorithm using partial and dynamic reconfiguration," INTEGRATION, the VLSI journal, vol. 43, pp. 72-80, 2010.
  7. R. F. Mirzaee, M. Eshghi, K. Navi, "Design and Implementation of an ASIP-Based Crypto Processor for IDEA and SAFER K-64," International Journal of Design, Analysis and Tools for Integrated Circuits and Systems (IJDATICS), vol. 3, p. 21, 2012.
  8. R. Chen, Z. Jia, Y. Li, H. Xia, X. Li, , "The application specific instruction processor for AES," in Electronics Computer Technology (ICECT), 2011 3rd International Conference on, 2011, pp. 394-396.
  9. B. Gladman, "A specification for Rijndael, the AES algorithm," at fp. gladman. plus. com/cryptography_technology/rijndael/aes. spec, vol. 3. 1, pp. 1-29, 2001.
  10. K. Gaj, P. Chodowiec, , "FPGA and ASIC implementations of AES," in Cryptographic Engineering, ed: Springer, 2009, pp. 235-294.
  11. J. M. Granado, M. A. Vega-Rodríguez, J. M. Sánchez-Pérez, J. A. Gómez-Pulido, , "IDEA and AES, two cryptographic algorithms implemented using partial and dynamic reconfiguration," Microelectronics Journal, vol. 40, pp. 1032-1040, 2009.
  12. M. M. Mano, Computer system architecture: Prentice-Hall Englewood Cliffs, NJ, 1993.
Index Terms

Computer Science
Information Sciences

Keywords

ASIP AES algorithm RTL crypto Processor

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