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Modified Two Phase Clocked Adiabatic Static CMOS Logic

by Swati Dhamani, Alka Agarwal, Praveer Saxena
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 93 - Number 18
Year of Publication: 2014
Authors: Swati Dhamani, Alka Agarwal, Praveer Saxena
10.5120/16437-6158

Swati Dhamani, Alka Agarwal, Praveer Saxena . Modified Two Phase Clocked Adiabatic Static CMOS Logic. International Journal of Computer Applications. 93, 18 ( May 2014), 32-39. DOI=10.5120/16437-6158

@article{ 10.5120/16437-6158,
author = { Swati Dhamani, Alka Agarwal, Praveer Saxena },
title = { Modified Two Phase Clocked Adiabatic Static CMOS Logic },
journal = { International Journal of Computer Applications },
issue_date = { May 2014 },
volume = { 93 },
number = { 18 },
month = { May },
year = { 2014 },
issn = { 0975-8887 },
pages = { 32-39 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume93/number18/16437-6158/ },
doi = { 10.5120/16437-6158 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:16:05.658669+05:30
%A Swati Dhamani
%A Alka Agarwal
%A Praveer Saxena
%T Modified Two Phase Clocked Adiabatic Static CMOS Logic
%J International Journal of Computer Applications
%@ 0975-8887
%V 93
%N 18
%P 32-39
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In the past decade, various adiabatic logic techniques have been proposed by various authors. One of the widely known adiabatic logic style is Two Phase Clocked Adiabatic Static CMOS Logic (2PASCL). The logic circuits based on 2PASCL suffer from floating output node due to alternate hold phase in its operation. Keeping a node floating for a long time may result in erroneous node voltage. In this paper a technique to reduce the floating node problem associated with 2PASCL is introduced. Modified 2PASCL is used to design a 2-input NAND gate, a 2-input NOR gate and 1- bit full adder at 45nm technology parameters provided by predictive technology and the circuits are simulated using HSPICE. The 2- input NAND gate designed with Modified 2PASCL is compared with the NAND gates designed with 2PASCL and Static CMOS in terms of average power consumed by them for different values of load capacitance and input frequency. NAND gates are also compared in terms of propagation delay, power delay product and the transistor count to implement them. It is observed that the NAND gate based on Modified 2PASCL offer up to 80. 3% power saving in comparison to NAND gate based on static CMOS and also exhibit least power delay product.

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Index Terms

Computer Science
Information Sciences

Keywords

Low Power Energy Recovery Floating Node.

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