The week's pick
Reseach Article
A High Speed Explicit Pulsed Dual Edge Triggered D Flip Flop
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 93 - Number 17 |
| Year of Publication: 2014 |
| Authors: Manan Joshi, D S Chauhan, B. K. Kaushik |
10.5120/16425-5607
|
Manan Joshi, D S Chauhan, B. K. Kaushik . A High Speed Explicit Pulsed Dual Edge Triggered D Flip Flop. International Journal of Computer Applications. 93, 17 ( May 2014), 5-9. DOI=10.5120/16425-5607
Abstract
This paper presents an efficient explicit pulsed static dual edge triggered flip flop with an improved performance. The proposed design overcomes the drawbacks of the dynamic logic family and uses explicit clock pulse generator approach to achieve dual edge triggering. The proposed flip-flop is compared with existing explicit pulsed dual edge triggered flip-flops. Based on the simulation results overall improvements of 12. 67% and 10. 15% are observed in delay and power delay product respectively.
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