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Low Power Domino Full Adder
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 93 - Number 10 |
| Year of Publication: 2014 |
| Authors: Payal Soni, Shiwani Singh |
10.5120/16255-5866
|
Payal Soni, Shiwani Singh . Low Power Domino Full Adder. International Journal of Computer Applications. 93, 10 ( May 2014), 40-43. DOI=10.5120/16255-5866
Abstract
With the advancement of technology, power consumption and higher speed becomes major concern for VLSI systems. In this paper, a new hybrid domino XOR is proposed and compared with existing domino XOR cell. As an application of proposed XOR cell, 1-bit full adder has been designed and compared with a full adder circuit using existing XOR cell. Both proposed designs XOR and full adder show better results in terms of power, delay and power-delay product. All the simulations have been performed on 45nm technology using tanner EDA tool version 13. 0.
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