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A Novel Power Reduction Technique for CMOS Circuits using Voltage Scaling and Transistor Gating
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 92 - Number 11 |
| Year of Publication: 2014 |
| Authors: Ankish Handa, Prateek Garg, Geetanjali Sharma |
10.5120/16056-5301
|
Ankish Handa, Prateek Garg, Geetanjali Sharma . A Novel Power Reduction Technique for CMOS Circuits using Voltage Scaling and Transistor Gating. International Journal of Computer Applications. 92, 11 ( April 2014), 38-42. DOI=10.5120/16056-5301
Abstract
The colossal portion of power in CMOS circuits is consumed during switching which is termed as dynamic power consumption. This absorbs more than 60% of the overall power in the circuit. However as the technology scales down, subthreshold leakage becomes commensurable to dynamic power dissipation. This happens as a result of reduction in threshold voltage and device geometry. In this brief, a high performance and power efficient technique is proffered which operates in subthreshold region. The proposed (VS-TG) technique curtails both dynamic and static power dissipation. The dynamic power dissipation is reduced by deploying Voltage Scaling technique while leakage or static power dissipation is lowered with Transistor Gating technique. The total power consumption is reduced by 30% to 90%. The proposed technique is implemented on 2-input NOR gate at different voltages at 10 °C, 20 °C and 30 °C. Tanner Tool EDA at 45nm process is used for simulation.
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