CFP last date
20 December 2024
Reseach Article

Low Power 3T XOR Cell using IDDG MOSFET

by Ruchika, Tripti Sharma, K. G. Sharma
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 91 - Number 7
Year of Publication: 2014
Authors: Ruchika, Tripti Sharma, K. G. Sharma
10.5120/15895-5065

Ruchika, Tripti Sharma, K. G. Sharma . Low Power 3T XOR Cell using IDDG MOSFET. International Journal of Computer Applications. 91, 7 ( April 2014), 38-40. DOI=10.5120/15895-5065

@article{ 10.5120/15895-5065,
author = { Ruchika, Tripti Sharma, K. G. Sharma },
title = { Low Power 3T XOR Cell using IDDG MOSFET },
journal = { International Journal of Computer Applications },
issue_date = { April 2014 },
volume = { 91 },
number = { 7 },
month = { April },
year = { 2014 },
issn = { 0975-8887 },
pages = { 38-40 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume91/number7/15895-5065/ },
doi = { 10.5120/15895-5065 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:12:10.270918+05:30
%A Ruchika
%A Tripti Sharma
%A K. G. Sharma
%T Low Power 3T XOR Cell using IDDG MOSFET
%J International Journal of Computer Applications
%@ 0975-8887
%V 91
%N 7
%P 38-40
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper, a new design of three transistor XOR gate is proposed using Independent Driven Double Gate MOSFET to achieve ultra-low power in sub threshold conduction. The proposed design has been compared with the three transistor XOR implemented using Symmetrical Driven Double Gate MOSFET in sub threshold region. A three transistor XOR gate designed using Independent Driven Double Gate MOSFET is showing improved results in terms of power consumption with varying input voltage, temperature and operating frequencies. The simulation has been carried out on SPICE tool at 45 nm technology.

References
  1. D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur and H. S. P. Wong, "Device Scaling Limits of Si MOSFETs and their application dependencies" Proceedings of the IEEE, vol. 89, iss. 3, Mar. 2001, pp. 259-288.
  2. S. K. Gupta, G. G. Pathak, D. Das and C. Sarma, "Design and Simulation of a Two Stage OP-AMP using DG MOSFETs for Low Power and Low voltage Applications," International Journal of Wisdom Based Computing, vol. 1, iss. 3, Dec. 2011, pp. 60-63.
  3. S. Abbasalizadeh and B. Forouzandeh, "Full Adder Design with GDI cell and Independent Double Gate Transistor," Iranian Conference on Electrical Engineering, (ICEE), May 2012, pp. 130-133.
  4. S. Mukhopadhyay, H. Mahmoodi and K. Roy, "A Novel High-Performance and Robust Sense Amplifier using Independent Gate Control in sub-50-nm Double Gate MOSFET," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 2, Feb. 2006, pp. 183-192.
  5. V. K. Yadav and A. K. Rana, "Impact of Channel Doping on DG-MOSFET Parameters in Nano Regime- TCAD Simulation," International Journal of Computer Applications, vol. 37, iss. 11, Jan. 2012, pp. 36-41.
  6. A. K. Shrivastava and S. Akashe, "Comparative Analysis of Low Power 10T and 14T Full Adder using Double Gate MOSFET at 45nm Technology," International Journal of Computer Applications, vol. 75, no. 3, Aug. 2013, pp. 48-52.
  7. M. Reyboz, O. Rozeau, T. Poiroux and P. Martin, Asymmetrical Double Gate (ADG) MOSFETs Compact Modeling, LETI-CEA, Grenoble, France, 2005, http://www. mosak. org/grenoble/slides/07_Rozeau_MOS-AK. pdf.
  8. S. R. Chowdhury, A. Banerjee, A. Roy, H. Saha, "A High Speed 8 Transistor Full Adder Design using Novel 3 Transistor XOR gates," World Academy of Science, Engineering and Technology, vol. 2, no. 10, 2008, pp. 685-691.
Index Terms

Computer Science
Information Sciences

Keywords

DG MOSFET low power sub threshold XOR gate.