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Design and FPGA Implementation of High Speed Vedic Multiplier
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 90 - Number 16 |
| Year of Publication: 2014 |
| Authors: Sudeep.m.c, Sharath Bimba.m, Mahendra Vucha |
10.5120/15802-4641
|
Sudeep.m.c, Sharath Bimba.m, Mahendra Vucha . Design and FPGA Implementation of High Speed Vedic Multiplier. International Journal of Computer Applications. 90, 16 ( March 2014), 6-9. DOI=10.5120/15802-4641
Abstract
Multiplication is an operation much needed in Digital Signal Processing for various applications. This paper puts forward a high speed Vedic multiplier which is efficient in terms of speed, making use of Urdhva Tiryagbhyam, a sutra from Vedic Math for multiplication and Kogge Stone algorithm for performing addition of partial products and also compares it with the characteristics of existing respective algorithms. The below two algorithms aids to parallel generation of partial products and faster carry generation respectively, leading to better performance. The code is written in Verilog HDL and implemented on Xilinx Spartan 3 and Spartan 6 FPGA kit using Xilinx ISE 9. 1i. The propagation delay of the implemented architecture is obtained to be 28. 699ns and 15. 752ns respectively.
References
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