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Application Specific Cache Simulation Analysis for Application Specific Instructionset Processor
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 90 - Number 13 |
| Year of Publication: 2014 |
| Authors: Ravi Khatwal, Manoj Kumar Jain |
10.5120/15782-4526
|
Ravi Khatwal, Manoj Kumar Jain . Application Specific Cache Simulation Analysis for Application Specific Instructionset Processor. International Journal of Computer Applications. 90, 13 ( March 2014), 31-41. DOI=10.5120/15782-4526
Abstract
An Efficient Simulation of application specific instruction-set processors (ASIP) is a challenging onus in the area of VLSI design. This paper reconnoiters the possibility of use of ASIP simulators for ASIP Simulation. This proposed study allow as the simulation of the cache memory design with various ASIP simulators like Simple scalar and VEX. In this paper we have implemented the memory configuration according to desire application. These simulators performs the cache related results such as cache name, sets, cache associativity, cache block size, cache replacement policy according to specific application.
References
- Jain, M. K. , Balakrishnan, M. and Kumar, A. 2005. Integrated on-chip storage evaluation in ASIP synthesis. VLSI Design, (2005), 274 - 279.
- Kin J. , Gupta, M. And Mangione-Smith, W. H. 2000. Filtering memory references to increase energy efficiency. IEEE transaction on computes . Vol. 49, (2000), 1-15.
- Vivekanadarajah, K. and Thambipillai, K. 2011 . Custom Instruction Filter Cache Synthesis for Low- Power Embedded systems. (2011).
- Shiue, W. T. 1999. Data Memory Design and Exploration for Low Power Embedded Systems. In proc of 36 th annual ACM/IEEE Design automation conference. (1999), 140-145.
- Prinkyl, Z. 2011 . Fast just in time translated simulator for ASIP design. IEEE 14th International symposium. (2011), 279-282.
- Simple scalar homepage: http://www. simplescalar. com
- Vex homepage: http://www. hpl. hp. com/downloads/vex/
- Gremzow, C. 2007. Compiled Low-Level Virtual Instruction Set Simulation and Profiling for Code Partitioning and ASIP-Synthesis in Hardware/Software Co-Design. (2007), 741-748.
- Fischer, D. , Teich, J. , Thies, M. , Weper, R. 2002. Efficient Architecture/Compiler Co-Exploration for ASIPs. (2002).
- Guzman, V. Bhattacharyya, S. S, Kellomaki, E. and Takala, J. 2009. An Integrated ASIP Design Flow for Digital Signal Processing Applications. (2009).
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