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Reseach Article

VLSI Implementation of Segmentation of Single Channel ECG

by S.preethi, M.jayasheela
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 90 - Number 13
Year of Publication: 2014
Authors: S.preethi, M.jayasheela
10.5120/15781-4515

S.preethi, M.jayasheela . VLSI Implementation of Segmentation of Single Channel ECG. International Journal of Computer Applications. 90, 13 ( March 2014), 27-30. DOI=10.5120/15781-4515

@article{ 10.5120/15781-4515,
author = { S.preethi, M.jayasheela },
title = { VLSI Implementation of Segmentation of Single Channel ECG },
journal = { International Journal of Computer Applications },
issue_date = { March 2014 },
volume = { 90 },
number = { 13 },
month = { March },
year = { 2014 },
issn = { 0975-8887 },
pages = { 27-30 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume90/number13/15781-4515/ },
doi = { 10.5120/15781-4515 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:10:57.806725+05:30
%A S.preethi
%A M.jayasheela
%T VLSI Implementation of Segmentation of Single Channel ECG
%J International Journal of Computer Applications
%@ 0975-8887
%V 90
%N 13
%P 27-30
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper the implementation of extraction of respiratory signal from ECG signal in very large scale integration (VLSI) using discrete wavelet transform (DWT) is discussed. The Indirect method to obtain the respiratory signal from ECG can benefit both respiratory and cardiac activities. The accuracy of the extracted respiratory signal will be high. The implementation is based on bit serial approach (BS) which substitute multiply and accumulate operations. BS provides a multiplication-free method for calculating inner products of fixed-point data. But increase in filter order leads complexity. Here we propose high-speed and low power architecture. The proposed method is implemented in hardware description language and verified via simulation. The proposed architecture scheme yields significantly reduced complexity, less area and high speed features.

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Index Terms

Computer Science
Information Sciences

Keywords

Finite impulse response (FIR) bit serial approach (BS) discrete wavelet transforms (DWT) very large scale integration (VLSI).