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Design of Multipath Delay Commutator Architecture based FFT Processor for 4th Generation Systems

by Amjadha.a, E.konguvel, J.raja
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 89 - Number 12
Year of Publication: 2014
Authors: Amjadha.a, E.konguvel, J.raja
10.5120/15683-4519

Amjadha.a, E.konguvel, J.raja . Design of Multipath Delay Commutator Architecture based FFT Processor for 4th Generation Systems. International Journal of Computer Applications. 89, 12 ( March 2014), 23-28. DOI=10.5120/15683-4519

@article{ 10.5120/15683-4519,
author = { Amjadha.a, E.konguvel, J.raja },
title = { Design of Multipath Delay Commutator Architecture based FFT Processor for 4th Generation Systems },
journal = { International Journal of Computer Applications },
issue_date = { March 2014 },
volume = { 89 },
number = { 12 },
month = { March },
year = { 2014 },
issn = { 0975-8887 },
pages = { 23-28 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume89/number12/15683-4519/ },
doi = { 10.5120/15683-4519 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:09:03.710634+05:30
%A Amjadha.a
%A E.konguvel
%A J.raja
%T Design of Multipath Delay Commutator Architecture based FFT Processor for 4th Generation Systems
%J International Journal of Computer Applications
%@ 0975-8887
%V 89
%N 12
%P 23-28
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The FFT/IFFT processor is widely used in various areas such as 4G telecommunications, speech and image processing, medical electronics and seismic processing, etc. In this paper an efficient implementation of FFT/IFFT processor for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) systems with variable length is presented. This paper opts memory scheduling and Multipath Delay Commutator (MDC) as the hardware architecture. Radix-Ns butterflies are used at each stage, where Ns denote the number of data streams, so that there is only one butterfly is used in each stage. For area and time optimization and to reduce power consumption, the Read Only Memories (ROM'S) which is used to store twiddle factor is replaced by complex multiplier. The design reduces the use of logic elements to 2. 21% from 10. 46% and achieves a maximum clock set up time of 3. 981ns (251. 19MHz) and worst case Tco of 49. 314ns. The result shows the advantages of the proposed scheme in terms of area and power consumption.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Fast Fourier transform (FFT) Memory scheduling Complex multiplier MIMO OFDM.

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