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Analysis of Low Power CMOS Current Comparison Domino Logic Circuits in Ultra Deep Submicron Technologies

by Gurjeet Kaur, Gurmohan Singh
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 88 - Number 7
Year of Publication: 2014
Authors: Gurjeet Kaur, Gurmohan Singh
10.5120/15368-3878

Gurjeet Kaur, Gurmohan Singh . Analysis of Low Power CMOS Current Comparison Domino Logic Circuits in Ultra Deep Submicron Technologies. International Journal of Computer Applications. 88, 7 ( February 2014), 44-49. DOI=10.5120/15368-3878

@article{ 10.5120/15368-3878,
author = { Gurjeet Kaur, Gurmohan Singh },
title = { Analysis of Low Power CMOS Current Comparison Domino Logic Circuits in Ultra Deep Submicron Technologies },
journal = { International Journal of Computer Applications },
issue_date = { February 2014 },
volume = { 88 },
number = { 7 },
month = { February },
year = { 2014 },
issn = { 0975-8887 },
pages = { 44-49 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume88/number7/15368-3878/ },
doi = { 10.5120/15368-3878 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:07:03.079995+05:30
%A Gurjeet Kaur
%A Gurmohan Singh
%T Analysis of Low Power CMOS Current Comparison Domino Logic Circuits in Ultra Deep Submicron Technologies
%J International Journal of Computer Applications
%@ 0975-8887
%V 88
%N 7
%P 44-49
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Performance of high fan–in Domino circuits is degraded by technology scaling due to exponential increase in leakage. To improve the performance Current Comparison Domino (CCD) circuits are widely used. This work presents design of wide fan-in high performance current comparison domino circuits with goals of minimizing the power dissipation and propagation delay at 90nm and 45nm ultra deep submicron (UDSM) technology nodes. A Current Comparison Domino (CCD) 32-input wide footless OR gate circuit is employed for design and analysis work. Cadence GPDK 90nm & 45nm model parameters are used in this research work. Cadence Virtuoso schematic editor is used to draw the schematic and Spectre circuit simulator is used for simulation work. Layouts are generated in Virtuoso Layout editor. Pre-layout and post- layout simulation results are compared for validation of results. At 45nm technology, the Power consumption is 718. 6nW, Propagation delay is 1. 450ns and Power delay product (PDP) is 1. 041fj. 92% improvement in power consumption at 45nm technology has been achieved as compared to previous work (at 16nm) by generating highly customized layout of the designed circuit.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Dynamic logic Static logic Domino logic UDSM CCD

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