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Design 2.4 GHz 130nm CMOS Low Noise Amplifier Design for Wireless Network
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 88 - Number 2 |
| Year of Publication: 2014 |
| Authors: Aniket Dhongde, Prashant Indurkar, Ravindra Kadam |
10.5120/15328-3646
|
Aniket Dhongde, Prashant Indurkar, Ravindra Kadam . Design 2.4 GHz 130nm CMOS Low Noise Amplifier Design for Wireless Network. International Journal of Computer Applications. 88, 2 ( February 2014), 47-50. DOI=10.5120/15328-3646
Abstract
A low noise amplifier is one of the most commonly used components in analog and digital circuit designs. Low voltage, low power and low noise amplifier design has become an increasingly interesting subject as many applications switch to portable battery powered operations. An amplifier is linear electronic circuits that may used amplify an input signal and provide an output signal that is a magnified replica of the input signal. The need for design techniques to allow amplifiers to maintain an acceptable level of performance when the supply voltages are decreased is immense for maintain high gain and as low as possible noise. Popular LNA topologies are the inductive source degeneration common-source low noise amplifier. The common source low noise amplifier is commonly used for narrow-band applications due to its ease of input matching, high gain and low noise. Using this method, overall gain can be increased and the noise figure of the low noise amplifier can be decreased. . This work we presents a design of a low noise CMOS amplifier realized in a standard 130 nm CMOS technology with 1. 3V supply voltage and consumes power less than 200uW with <1. 5mA current. A two stage cascode LNA has to achieved noise figure is less than 2. 5dB and achieves a gain >18dB on given frequency range also have good input and output matching.
References
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