The week's pick
Random Articles
Reseach Article
Design and Analysis of Area and Power Efficient 1-Bit Full Subtractor using 120nm Technology
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 88 - Number 12 |
| Year of Publication: 2014 |
| Authors: Pranshu Sharma, Anjali Sharma, Richa Singh |
10.5120/15408-3978
|
Pranshu Sharma, Anjali Sharma, Richa Singh . Design and Analysis of Area and Power Efficient 1-Bit Full Subtractor using 120nm Technology. International Journal of Computer Applications. 88, 12 ( February 2014), 36-42. DOI=10.5120/15408-3978
Abstract
In this paper an area and power efficient 14T 1-bit Full Subtractor design has been presented by using GDI techniques. The proposed 1-bit Subtractor design consist of 7 NMOS and 7 PMOS. For difference output of 1-bit full Subtractor GDI XOR-XNOR module outputs has been used with GDI 2x1 MUX. A GDI XOR- XNOR module has been used which consume less area at 120 nm as compared with the previous XOR-XNOR modules. The proposed GDI 1- bit Full Subtractor design is based on this area efficient 6T XOR-XNOR module. To improve area and power efficiency a cascade implementation of XOR module has been avoided in the used 1-bit GDI Full Subtractor module. Difference block of this 1-Bit Full Subtractor module has been implemented by 8 transistors only. The proposed 1-bit Full Subtractor has been designed and simulated using DSCH 3. 1 and Microwind 3. 1 on 120nm. Also the simulation of layout and parametric analysis has been done for the proposed 1-bit GDI Full Subtractor design. Power variation with respect to the supply voltage has been performed on BSIM-4 and LEVEL-3 on 120nm. Results show that area consumed by the proposed 1-Bit GDI Full Subtractor is 263. 1?m2 on 120nm technology. At 1. 2V input supply voltage the proposed 1-bit GDI Full Subtractor consume 7. 697µW power at BSIM-4 and 7. 708µW power at LEVEL-3. Also the proposed 1-bit GDI Full Subtractor has been compared with other Subtractor designs by CMOS, TG and PTL logic and the proposed design has been proved both area and power efficient as compared to design by other logics.
References
- Sung-Mo Kang, Yusuf Leblebici, (2003) CMOS Digital Integrated Circuits: Analysis and Design TATA McGRAW-HILL.
- Anjali Sharma, Richa Singh, Rajesh Mehra, Member IEEE, "Low Power TG Full Adder Design Using CMOS Nano Technology," IEEE International Conference on Parallel, Distributed and Grid Computing, pp. 210-213, 2012.
- Anjali Sharma, Richa Singh, Pankaj Kajla "Area Efficient 1-Bit Comparator Design by using Hybridized Full Adder Module based on PTL and GDI Logic," International Journal of Computer Applications, Vol. 82, No. 10, pp. 5-13.
- N. Weste and K. Eshraghian, (2002) Principles of CMOSVLSI Design: A System Perspective Reading, Pearson Education, Addison–Wesley.
- Anil K. Maini, (2012), " Digital Electronics Principles and Integrated Circuits" pp. 209-213.
- Tanvi Sood, Rajesh Mehra, " Design a Low Power Half-Subtractor Using . 90?m CMOS Technology," IOSR Journal of VLSI and Signal Processing , Vol. 2, No. 3 , pp. 51-56.
- B. Dilli Kumar, M. Bharathi, "Design and Analysis of Adaiabatic Full Subtractor for Low Power Applications", International Journal of Advanced Scientific and Technical Research, Vol. 1, No. 3, pp. 219-231.
- Microwind and DSCH version 3. 1, User's Manual, Copyright 1997-2007, Microwind INSA France, pp. 97-103, 2006.
Index Terms
Keywords