The week's pick
Reseach Article
Power Efficient Design of Polar Code
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 87 - Number 7 |
| Year of Publication: 2014 |
| Authors: Sapna R. Makvana, Brijesh Vala |
10.5120/15223-3735
|
Sapna R. Makvana, Brijesh Vala . Power Efficient Design of Polar Code. International Journal of Computer Applications. 87, 7 ( February 2014), 35-39. DOI=10.5120/15223-3735
Abstract
Polar codes are the family of the codes which are first ones to achieve channel capacity of any binary discrete memory less channel (B-DMC) with an explicit construction. The method relates with polar codes, channel polarization and encoding & decoding of polar code is considered that in the live structure of polar code when BER gets increase, channel capacity is satisfied but overall power of data transmition in channel gets increase. So here in this analysis the main issue is related with the power consumption. Encoding & decoding construction of polar codes is based on XOR-XNOR gates. The XOR-XNOR circuits' design which uses 6 transistors instead of conventional structure is designed and it is suitable for low-voltage and low-power application by achieving lower delay, power consumption and power-delay product (PDP). So by using this design phenomenon of XOR-XNOR gate it is possible to construct power efficient encoding and decoding of polar codes.
References
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