The week's pick
Random Articles
Reseach Article
A Novel High Performance Low Power Universal Gate Implementation in Subthreshold Region
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 87 - Number 12 |
| Year of Publication: 2014 |
| Authors: Ankish Handa, Paanshul Dobriyal, Geetanjali Sharma |
10.5120/15261-3938
|
Ankish Handa, Paanshul Dobriyal, Geetanjali Sharma . A Novel High Performance Low Power Universal Gate Implementation in Subthreshold Region. International Journal of Computer Applications. 87, 12 ( February 2014), 21-25. DOI=10.5120/15261-3938
Abstract
In any integrated circuit power consumption plays a paramount role and is considered as one of the top challenges in International technology roadmap for semiconductors. In this paper, a low power circuit designed to operate in subthreshold region is proposed. Voltage scaling technique is incorporated to reduce dynamic power consumption while static or leakage power is greatly reduced with forced stack technique. The present technique (VS-STACK) features very low power dissipation as compared to its standard CMOS counterparts in subthreshold region. The power consumption is curtailed by 20% to 90% together with a better power delay product (PDP) over a supply voltage range. The technique is tested on a 2-input NOR gate in the 45nm process. Tanner Tool EDA 13. 0v is used for simulation.
References
- Hendrawan Soeleman and Kaushik Roy,"Ultra-Low Power Digital Subthreshold Logic Circuits," in International Symposium on Low Power Electronics and Design, 1999, pp. 94-96.
- Hendrawan Soleleman, Kaushik Roy and Bipul Paul, "Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic," in 14th International Conference on VLSI Design, 2001, pp. 211-214.
- Manan Sethi, Karna Sharma, Paanshul Dobriyal, Navya Rajput, Geetanjali Sharma ,"A Novel High Performance Dual Threshold Voltage Domino Logic Employing Stacked Transistors," International Journal of Computer Applications(0975-8887), vol. 77- No. 5, September 2013.
- M. Johnson, D. Somasekhar, L-Y Chiou and K. Roy , "Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS," IEEE Trans. VLSI Systems, vol. 10, 2002, pp. 1-5.
- Yu-Tzu Tsai, Hsiang-Hui Huang, Shang-Wei Hsu Ching- Hwa Chang, *Jiun-In Guo ,"A Low-Power VDD-Management Technique For High-Speed Domino Circuits," in International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2011, pp. 1-4.
- Arun. P, Ramasamy. S ,"A Low-Power Dual Threshold Voltage-Voltage Scaling Technique for Domino Logic Circuits," in Proc. ICCNT, 2012, pp. 1-6.
- K. Agarwal, H. Deogun, D. Sylvester, and K. Nowka , "Power gating with multiple sleep modes," in Proc. 7th International Symposium on Quality Electronic Design, March 2006, pp. 633– 637.
- T. Douseki, S. Mutoh, Y. Matsuya, T. Aoki, S. Shigematsu and J. Yamada,"1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," IEEE Journal of Solid-State Circuits, pp. 847-854, 1995.
- Q. Wang, and S. Vrudhula,"Static power optimization of deep submicron CMOS circuits for dual Vt technology," Proceedings of ICCAD, pp. 490–496, April 1998.
- Karna Sharma, Manan Sethi, Paanshul Dobriyal, Geetanjali Sharma ,"Designing a Novel Power Efficient D-Flip Flop using Forced Stack Technique," International Journal of Computer Applications(0975-8887), vol. 68- No. 9, April 2013.
Index Terms
Keywords