We apologize for a recent technical issue with our email system, which temporarily affected account activations. Accounts have now been activated. Authors may proceed with paper submissions. PhDFocusTM
CFP last date
20 November 2024
Call for Paper
December Edition
IJCA solicits high quality original research papers for the upcoming December edition of the journal. The last date of research paper submission is 20 November 2024

Submit your paper
Know more
Reseach Article

FPGA Implementation of Latency, Computational time Improvements in Matrix Multiplication

by Shriyashi Jain, Neeraj Kumar, Jaikaran Singh, Mukesh Tiwari
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 86 - Number 8
Year of Publication: 2014
Authors: Shriyashi Jain, Neeraj Kumar, Jaikaran Singh, Mukesh Tiwari
10.5120/15007-3261

Shriyashi Jain, Neeraj Kumar, Jaikaran Singh, Mukesh Tiwari . FPGA Implementation of Latency, Computational time Improvements in Matrix Multiplication. International Journal of Computer Applications. 86, 8 ( January 2014), 27-29. DOI=10.5120/15007-3261

@article{ 10.5120/15007-3261,
author = { Shriyashi Jain, Neeraj Kumar, Jaikaran Singh, Mukesh Tiwari },
title = { FPGA Implementation of Latency, Computational time Improvements in Matrix Multiplication },
journal = { International Journal of Computer Applications },
issue_date = { January 2014 },
volume = { 86 },
number = { 8 },
month = { January },
year = { 2014 },
issn = { 0975-8887 },
pages = { 27-29 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume86/number8/15007-3261/ },
doi = { 10.5120/15007-3261 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:03:42.441417+05:30
%A Shriyashi Jain
%A Neeraj Kumar
%A Jaikaran Singh
%A Mukesh Tiwari
%T FPGA Implementation of Latency, Computational time Improvements in Matrix Multiplication
%J International Journal of Computer Applications
%@ 0975-8887
%V 86
%N 8
%P 27-29
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Matrix operations, like matrix multiplication, are commonly used in almost all areas of scientific research. Matrix multiplication has significant application in the areas of graph theory, numerical algorithms, signal processing, and digital control. Matrix multiplication is a computationally intensive problem, especially the design and efficient implementation on an FPGA where resources are very limited, has been more demanding. FPGA based designs are usually evaluated using three performance metrics: speed (latency), area, and power (energy). Fixed point implementations in FPGA are fast and have minimal power consumption. With today's applications requiring ever higher computational throughputs, distributed memory approach is an effective solution for real-time applications. This application shows how to achieve higher computational throughput via parallel processing with the DSP processors. The matrix-vector multiplication applied to calculate linear convolution. This paper presents an FPGA-based hardware realization of matrix multiplication based on distributed memory approach architecture. We propose an architecture that is capable of handling matrices of variable sizes our designs minimize the gate count, area, improvements in latency, computational time, and throughput for performing matrix multiplication and reduces the number of multiplication and additions hardware required to get the matrices multiplied on commercially available FPGA devices.

References
  1. Syed M. Qasim, Shuja A. Abbasi, "Throughput Latency Implementation of Matrix Multiplication using Field Programmable Gate Array" IEEE Transaction on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 6, Nov. 2012.
  2. Shu-Qing Li, Chi Hou Chan, Leung Tsan "Parallel Implementation of the Sparse- Matrix/Canonical Grid Method for the Analysis of Two-Dimensional Random Rough Surfaces (Three-Dimensional Scattering Problem) on a Beowulf System "IEEE Transaction on Geo Science and Remote Sensing, vol. 38, no. 4, July 2000.
  3. Davide Anastasia and Yiannus Andreopoulos, "Throughput-Distortion Computation Generaic Matrix Multiplication: Toward A Computation Channel for Digital Signal Processing System" IEEE Transaction on Signal Processing, vol. 60, no. 4, April 2012.
  4. Nan Zhang "A Novel Parallel Scan for Multicore Processors and Its Application in Sparse Matrix-Vector Multiplication" IEEE Transaction on Parallel and Distributed System, vol. 23, on. 3, March 2012.
  5. Bahram Hamraz, Nicholas HM Caldwell, and P. John Clarkson "A Matrix-Calculation-Based Algorithm for Numerical Change Propagation Analysis" IEEE Transaction on Engineering Management, vol. 60, no. 1, February 2013.
  6. Vasileios Karakasis, Theodoros Gkountouvas, Kornilios Kourtis, Georgios Goumas, Nectarios Koziris "An Extended Compression Format for the Optimization of Sparse Matrix-Vector Multiplication" IEEE Transaction on Parallel and Distributed System- 2012.
Index Terms

Computer Science
Information Sciences

Keywords

Latency computational throughput gate count field-programmable gate array (FPGA).