We apologize for a recent technical issue with our email system, which temporarily affected account activations. Accounts have now been activated. Authors may proceed with paper submissions. PhDFocusTM
CFP last date
20 November 2024
Call for Paper
December Edition
IJCA solicits high quality original research papers for the upcoming December edition of the journal. The last date of research paper submission is 20 November 2024

Submit your paper
Know more
Reseach Article

Strategies and Techniques for Optimizing Power in BIST: A Review

by Amandeep Singh, P. Mohan Kumar, Mohinder Bassi
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 86 - Number 4
Year of Publication: 2014
Authors: Amandeep Singh, P. Mohan Kumar, Mohinder Bassi
10.5120/14976-3175

Amandeep Singh, P. Mohan Kumar, Mohinder Bassi . Strategies and Techniques for Optimizing Power in BIST: A Review. International Journal of Computer Applications. 86, 4 ( January 2014), 38-42. DOI=10.5120/14976-3175

@article{ 10.5120/14976-3175,
author = { Amandeep Singh, P. Mohan Kumar, Mohinder Bassi },
title = { Strategies and Techniques for Optimizing Power in BIST: A Review },
journal = { International Journal of Computer Applications },
issue_date = { January 2014 },
volume = { 86 },
number = { 4 },
month = { January },
year = { 2014 },
issn = { 0975-8887 },
pages = { 38-42 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume86/number4/14976-3175/ },
doi = { 10.5120/14976-3175 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:03:22.182527+05:30
%A Amandeep Singh
%A P. Mohan Kumar
%A Mohinder Bassi
%T Strategies and Techniques for Optimizing Power in BIST: A Review
%J International Journal of Computer Applications
%@ 0975-8887
%V 86
%N 4
%P 38-42
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Power dissipation is a challenging problem in current VLSI designs. In general the power consumption of device is more in the testing mode than in the normal system operation. Built in self test (BIST) and scan-based BIST are the techniques used for testing and detecting the faulty components in the VLSI circuit. Linear Feedback Shift Register (LFSR) in BIST generates pseudo-random patterns for detecting the faults, increasing the power consumption during testing, boosting the need to add power optimizations to BIST pattern generators. This paper identifies the different techniques to modify the BIST architecture thereby finding an optimal choice to reduce power consumption without compromising upon fault coverage.

References
  1. Bellos Maciej, Bakalis Dimitris and Nikolos Dimitris, "Scan Cell Ordering for Low power BIST" in Proceedings of the IEEE Computer Society Annual Symposium on VLSI Emerging Trends in VLSI Systems Design, 2004.
  2. Cao Bei, Xiao Liyi and Wang Yongsheng, "A Low Power Deterministic Test Pattern Generator for BIST Based on Cellular Automata" in 4th IEEE International Symposium on Electronic Design, Test & Applications, pp. 266-268, 2008.
  3. Enmin Tan, Shengdong Song and Wenkang Shi, "Power Reduction in BIST Design Based on Genetic Algorithm and Vector-Inserted TPG" in The Eighth International Conference on Electronic Measurement and Instruments, pp. 533-537,2007.
  4. Ghosh Debjyoti, Bhunia Swarup and Roy Kaushik, "A Technique to Reduce Power and Test Application Time in BIST", in Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS'04),2004.
  5. Girard P. , Guiller L. , Landrault C. and Pravossoudovitch S. , "Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures" in ITC International Test Conference, pp. 652-661, 2000.
  6. Girard P. , Guiller L. , Landrault C. and Pravossoudovitch S. , "An Adjacency-Based Test Pattern Generator for Low Power BIST Design", IEEE, pp. 459-464, 2000.
  7. Kilic Hurevren and Oktem Levent, "Low-Power Test Pattern Generator Design for BIST via Non Uniform Cellular Automata" in IEEE, pp. 212-215, 2005.
  8. undu S. and Chattopadhyay S. , "Embedding a Low Power Test Set for Deterministic BIST using a Gray Counter", in Proceedings of the World Congress on Engineering, Vol II, July 6-8, WCE-2011.
  9. Lai Nan-Cheng, Wang Sying-Jyan and Fu Yu-Hsuan, "Low Power BIST with Smoother and Scan-Chain Reorder" in Asian Test Symposium, 2004.
  10. Lee Jinkyu and Touba Nur A. , "Low Power BIST Based on Scan Partitioning", in International Symposium on Defect and Fault Tolerance in VLSI Systems, IEEE 2005.
  11. Li Ji, Han Yinhe, Li Xiaowei, "Deterministic and Low Power BIST Based on Scan Slice Overlapping", IEEE, pp. 5670-5673, 2005.
  12. Manich S. , Gabarro A. , Lopez M. , Figueras J. , Girard P. , Guiller L. , Landrault C. , Pravossoudovitch S. , Teixeira P. and Santos M. , "Low Power BIST by filtering Non-Detecting Vectors," in Proc. European Test Workshop (ETW'99), pp. 165-170, 1999.
  13. M. Banu Fahmitha and N. Poornima, " BIST using genetic algorithm for error detection and correction" in IEEE- International Conference on Advances In Engineering , Science and Management (ICAESM-2012), pp. 588-592,March 30,31,2012.
  14. Nayineni Prathyusha and Masthan S. K, "Power optimization of BIST circuit using low power LFSR" in International Journal of Computer Trends and Technology, vol 2 Issue 2,pp. 5-8, 2011.
  15. Nemati Nastaran, Simjour Amirhossein, Ghofrani Amirali and Navabi Zainalabedin, "Optimizing Parametric BIST Using Bio-inspired Computing Algorithms", in 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 268-276, 2009.
  16. P. Sakthivel, NirmalKumar A. and Mayilsamy T. , "Low Transition Test Pattern Generator Architecture for Built-in-Self-Test" in American Journal of Applied Sciences, pp. 1396-1406,2012.
  17. Parashar Umesh, "Improved Low Power Full Scan BIST", IEEE, pp. 1103-1106, 2007.
  18. Reddy C. Ravishankar, Zilani Shaik and Sumalatha V. , "Low Power, Low Transition Random Pattern Generator" in International Journal of Engineering Research and Technology (IJERT), Vol 1 Issue 5, pp. 1-6, July-2012.
  19. Sato Yasuo, Wang Senling, Kato Takaaki, Miyase Kohei and Kajihara Seiji," Low Power BIST for Scan-Shift and Capture Power" in IEEE 21st Asian Test Symposium, pp. 173-178, 2012.
  20. Tan Enmin and Wang Li, "A BIST design with Low Power Consumption Based on Genetic Algorithm" in The Ninth International Conference on Electronic Measurement and Instruments, pp. 2-526 - 2-529, ICEMI'2009.
  21. Voyiatzis I. , Axiotis K. , Papaspyrou N. , Antonopoulou H. and Efstathiou C. , "Test Set Embedding Into Low-power BIST Sequences using Maximum Bipartite Matching", in 16th Pan-Hellenic Conference on Informatics, pp. 74-79, 2012.
  22. Xiao Liyi, Cao Bei, and Wang Yongsheng, "Seeds Optimization Algorithm of SIC Test sequences in Low Power BIST" in IEEE, 2010.
  23. Zhang Xiaodong, Shan Wenlei and Roy Kaushik, " Low-Power Weighted Random Pattern Testing", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 11, November 2000.
Index Terms

Computer Science
Information Sciences

Keywords

BIST scan based-BIST LFSR VLSI fault coverage.