The week's pick
Random Articles
Reseach Article
Optimization of Delay and Energy in On-Chip Buses using Bus Encoding Technique
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 86 - Number 12 |
| Year of Publication: 2014 |
| Authors: Souvik Singha, G. K. Mahanti |
10.5120/15035-3376
|
Souvik Singha, G. K. Mahanti . Optimization of Delay and Energy in On-Chip Buses using Bus Encoding Technique. International Journal of Computer Applications. 86, 12 ( January 2014), 7-12. DOI=10.5120/15035-3376
Abstract
In very deep sub-micron (VDSM) fault-tolerant busses, crosstalk noise and logic faults caused due to shrinking wire- size and reduced inter-wire spacing are major factors affecting the performance of on- chip interconnects, such as high power consumption and increased delay. In this paper we propose a bus optimization technique which reduce the energy and power-delay using Hamming Single Error Correcting Code. In this coding scheme we implement Fibonacci representation of optimal (7,4) Hamming Code which is more efficient than Single Error correction (9,4) Hamming Code. Also the proposed scheme eliminates crosstalk classes among the interconnects wires, there by reducing delay and energy consumption. The proposed techniques achieves an efficiency of 11% in energy consumption and a reduction of delay with respect to the existing techniques.
References
- D. ROSSI, V. E. S. van Dijk, R. P. Kleihorst, A. H. Nieuwland, C. Metra, "coding Scheme for low energy consumption fault-Tolerant Bus". Processing of the Eight IEEE International On-Line Testing Workshop (IOLTW' 02).
- C. Duan and S. P. Khatri, 2004. "Exploting crosstalk to speed up on-chip buses". Processing on the Conference on Design Automation and Test in Europe, pp. 777-783.
- J. Yim and C. Kung, 1999. "Reducing Cross-coupling among interconnect wires in deep-submicron data path design", Processing of the 36th ACM/IEEE conference on Design Automation, pp. 485-490.
- Sachin Sapatnekar, 2004. "Timing", Kluwer Publisher.
- S. Ramprasad, N. R. Shambhag, and I. N. Hajj, 1999. "A Coading Framework for Low-Power Address and Data Busses", IEEE Trans. On VLSI Systems.
- A. Kazeminejad, 2001. "Fast, Minimal Decoding Complexity systematic (13,8) Single-Error-Correcting code for on-chip DRAM Application", Electronic Letters.
- P. P. sotriadis and A. Chandrakasan, 2000. "Bus Energy Minimization by Transition Pattern Coding in Deep Submicron Technologies". In IEEE/ACM Int. Conference on Computer Aided Design, ICCAD, pp. 322-327.
- B. Victor, B. Keutzer, 2001. "Bus encoding to prevent crosstalk delay", In IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 57-63.
- M. R. Stan, W. P. Burleson, 1997. "Low-power encodings for global communication in CMOS VLSI", IEEE Trans on VLSI (TVLSI) 5(4), pp. 444-455.
- M. R. Stan, W. P. Burleson, 1995. "Bus-invert coding for low-power I/O. IEEE Trans. On VLSI (TVLSI), pp. 49-58.
- Y. shin, S. chae, K. Choi, 2001. "Partial Bus-invert coding for power Optimization of application-specific systems. IEEE Trans. On VLSI 9(2), pp. 377-383.
- Y. Zhang, J. Lach, K. Skadron, M. R. Stan, 2002. "Odd/even bus invert with two-phase transfer for buses with coupling", In: International Symposium on Low Power Electronics and Design (ISLPEd), pp. 80-83.
- S. Jayaprakash, N. R. mahapatra, 2007. " Partitioned hybrid encoding to minimize on-chip energy dissipation of wide microprocessor buses"' In: 20th Intl. Conf. on VLSI Design, pp. 127-134.
- K. H. Beak, K. W. Kim, S. M. Kang, 2000. "A low energy encoding technique for reducing of coupling effects in SOC interconnects", In: 43rd IEEE Midwest Symposium Circuits and Systems, pp. 80-83.
- P. Subrahmanya, R. Manimegalai, V. Kamakoti, M. Mutyam, 2004. "A busencoding technique for power and cross-talk minimization", In: 17th Intl. Conf. on VLSI Design, pp. 443-448.
- M. Lampropoulos, B. M. AI-Hashimi, P. Rosinger, 2004. " Minimization of crosstalk noise, delay and power using a modified bus invert technique:, In: Design, Automation and Test in Europe conference and Exhibition (DATE), vol 2, pp. 1372-1373.
- G. Chen, S. Duvall, S. Nooshabadi, 2009. "Analysis and design of memoryless interconnect Encoding scheme"' In: IEEE International Symp. On Circuits and Systems (ISCAS), pp. 2990-2993.
- C. J. Akl, M. A. Bayoumi, 2008. "Transition Skewing Coding for Global On-Chip Interconnects", IEEE Trans. On VLSI Systems 16(8), pp. 1091-1096.
- P. P. sotiriadis, A. Chandrakasan, 2001. "Reducing bus delay in submicron technology using coding", In: Asia South Pacific Design Automation (ASP-DAC), pp. 1280-1283.
- Y. Zhang, L. Huawei, L. Xiaowei, Y. Hu, 2008. "Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects", In: 26th IEEE VLSI Test Symp (IEEE-VTS), pp. 377-382.
- P. Sotiriadis and A. Chandrakasan, 2001. "Reducing bus delay in sub-micron technology using coding", Proceedings of the Asia and South Pacific Design Automation Conference, pp. 109-114.
- P. Sotiriadis and A. Chandrakasan, 2002. "A bus energy model for deep sub-micron technology", IEEE transactions on VLSI System, vol. 10(3), pp. 341350.
- P. Sotiriadis and A. Chandrakasan, 2002. "Low power bus encoding techniques considering inter-wire capacitances", Processing of the IEEE International Conference Custom Integrated Circuits, pp. 507-510.
- T. K. Moon, 2005. 'Error Correction Coding: Mathematical Methods and Algorithms", Wiley-Interscience.
- K. Najeeb, Vishal Gupta, V. kamakoti, Madhu Mutyam. "Temporal Redundency Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses", Publications. cse. iitm. ac. in.
Index Terms
Keywords