International Journal of Computer Applications |
Foundation of Computer Science (FCS), NY, USA |
Volume 86 - Number 11 |
Year of Publication: 2014 |
Authors: Amit Kumar, Shankar, Neeraj Sharma |
10.5120/15029-3347 |
Amit Kumar, Shankar, Neeraj Sharma . Verification of Asynchronous FIFO using System Verilog. International Journal of Computer Applications. 86, 11 ( January 2014), 16-20. DOI=10.5120/15029-3347
As the designs gets complex, the probability of occurrence of bugs increases. This necessitated the introduction of the verification phase for verifying the functionality of the IC and to detect the bugs at an early stage. In this paper, the Asynchronous FIFO design is verified using SystemVerilog. The design uses a grey code counter to address the memory and for the pointer.