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Design of Efficient Reversible Multiply Accumulate (MAC) Unit

by Rangaraju H G, Arpitha H S, Muralidhara K N
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 85 - Number 16
Year of Publication: 2014
Authors: Rangaraju H G, Arpitha H S, Muralidhara K N
10.5120/14922-3338

Rangaraju H G, Arpitha H S, Muralidhara K N . Design of Efficient Reversible Multiply Accumulate (MAC) Unit. International Journal of Computer Applications. 85, 16 ( January 2014), 1-12. DOI=10.5120/14922-3338

@article{ 10.5120/14922-3338,
author = { Rangaraju H G, Arpitha H S, Muralidhara K N },
title = { Design of Efficient Reversible Multiply Accumulate (MAC) Unit },
journal = { International Journal of Computer Applications },
issue_date = { January 2014 },
volume = { 85 },
number = { 16 },
month = { January },
year = { 2014 },
issn = { 0975-8887 },
pages = { 1-12 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume85/number16/14922-3338/ },
doi = { 10.5120/14922-3338 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:02:35.948328+05:30
%A Rangaraju H G
%A Arpitha H S
%A Muralidhara K N
%T Design of Efficient Reversible Multiply Accumulate (MAC) Unit
%J International Journal of Computer Applications
%@ 0975-8887
%V 85
%N 16
%P 1-12
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The multiplication and accumulation are the vital operations involved in almost all the Digital Signal Processing applications. Consequently, there is a demand for high speed processors having dedicated hardware to enhance the speed with which these multiplications and accumulations are performed. In the present conventional circuits, the multiply accumulate unit multiplies the two operands, adds the product to the previously accumulated result and stores back the new result in the accumulator all in a single clock cycle. On the other hand, using reversible logic the implementation of digital circuits is gaining popularity with the arrival of quantum computing and reversible logic. In this paper, a novel reversible multiply accumulate unit is proposed. the comparison of various possible implementations of the reversible multiply accumulate unit in terms of gate count, quantum cost, constant inputs and number of garbage outputs is carried out.

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Index Terms

Computer Science
Information Sciences

Keywords

Reversible Multiply Accumulate Unit Digital Signal Processors Reversible Shift Register Reversible Adder Reversible Multiplier Quantum Cost.

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