The week's pick
Reseach Article
Verification IP for Routing Switch based on Network Layer Protocol, using SystemVerilog
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 85 - Number 11 |
| Year of Publication: 2014 |
| Authors: Dipti Girdhar, Neeraj Sharma, Shankar |
10.5120/14888-3323
|
Dipti Girdhar, Neeraj Sharma, Shankar . Verification IP for Routing Switch based on Network Layer Protocol, using SystemVerilog. International Journal of Computer Applications. 85, 11 ( January 2014), 33-37. DOI=10.5120/14888-3323
Abstract
Today, in the world of ASICs and system-on-chip (SoC) designs which consists of millions of transistors and gates, verification is the process which consumes most of design efforts and time [4]. One of the major stresses for the verification engineer is to verify the given design in best possible manner [5]. For this he needs to cover almost all the hidden corners cases by applying various real time test cases. This paper will assist the verification engineers to understand the flow of verification environment for packet switch IP. We will also learn about the functional coverage. The language used for verification is SystemVerilog.
References
- Chris Spear, Greg Tumbush, Verification Guidelines, SystemVerilog for Verification, Third Edition (Ney York: Springer), pp. 58.
- Chris Spear, Greg Tumbush, Verification Guidelines, SystemVerilog for Verification, Third Edition (Ney York: Springer), pp. 61.
- Chris Spear, Greg Tumbush, Verification Guidelines, SystemVerilog for Verification, Third Edition (Ney York: Springer), pp. 62
- Purvi D. Mulani, "SoC Level Verification using SystemVerilog," In the proceedings of Emerging Trends in Engineering and Technology (ICETET) Conference, Nagpur, pp. 378-380, Dec. 2009
- Young-Jin Oh Gi-Yong Song, "Simple hardware verification platform using SystemVerilog," In the proceedings of TENCON 2011 - 2011 IEEE Region 10 Conference, Bali, pp. 1414 – 1417, Nov. 2011.
- Ma Pei-Jun, Ma Wen-Bo, Li Kang, Shi Jiang-Yi, others, "The verification of network processor Fast Bus Interface using SystemVerilog," In the proceedings of Electron Devices and Solid-State Circuits (EDSSC), 2011 International Conference, Tianjin, pp. 1 – 2, Nov. 2011.
- Simmons, M. , Geishauser, J. , "FlexBench: reuse of verification IP to increase productivity," In the proceedings of Design, Automation and Test in Europe Conference and Exhibition, Paris, 2002.
- Chia-Chih Yen, Jing-Yang Jou, An-Che Cheng, "A formal method to improve SystemVerilog functional coverage," In the proceedings of High Level Design Validation and Test Workshop (HLDVT), 2012 IEEE International Conference, Huntington Beach, CA, pp. 56 – 63, 9 – 10 Nov. 2012,
- Young-Jin Oh, Gi-Yong Song, Jae-Jin Lee, "Design and verification of an application-specific PLD using VHDL and SystemVerilog," In the proceedings of ASIC (ASICON), 2011 IEEE 9th International Conference, Xiamen, pp. 159 – 162, 25 – 28 Oct. 2011,
- Pierres, A. Hu Shiqing, Chen Fang and others, "Practical and efficient SOC verification flow by reusing IP testcase and testbench," In the proceedings of SoC Design Conference (ISOCC), 2012 International Conference, Jeji Island, pp. 175 – 178, 4 – 7 Nov. 2012
Index Terms
Keywords