The week's pick
Random Articles
Reseach Article
Design and Simulation of a Low Power Viterbi Decoder using Constraint Length Nine
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 84 - Number 2 |
| Year of Publication: 2013 |
| Authors: A. Mallaiah, K. Lakshmi Narayana, A. Jaya Lakshmi |
10.5120/14550-2638
|
A. Mallaiah, K. Lakshmi Narayana, A. Jaya Lakshmi . Design and Simulation of a Low Power Viterbi Decoder using Constraint Length Nine. International Journal of Computer Applications. 84, 2 ( December 2013), 24-27. DOI=10.5120/14550-2638
Abstract
Viterbi Decoder is the dominant module to determining the power consumption of the system. High speed and low power design of Viterbi Decoder with data rate1/2 and convolution encoding with a constraint length K = 9 is presented in this paper. The Proposed Viterbi decoder can be reduce the power consumption without reducing the decoding speed and also increases the length of the bits. The operating frequency of convolution encoder and Viterbi decoded is 306. 65MHz and power consumption is 45. 01Mw using Xpower tools in Xilinx and Spartan 3E FPGA kit.
References
- A. J. Viterbi, ?Error bounds for convolutional codes and an asymptotically optimum decodingalgorithm,? IEEE Transactions on Information Theory, vol. 13, no. 2, pp. 260–269, April 1967.
- G. Fettweis and H. Meyr. , ?Parallel Viterbi decoding by breaking the compare select feedbackbottleneck,? Communications, vol. 201, no. 88, 1988.
- J. He, Z. Wang, and H. Liu, "An efficient 4-D 8PSKTCM decoder architecture," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 18, no. 5, pp. 808–817, May 2010.
- Jinjin He, Huaping Liu, Zhongfeng Wang, Xinming Huang, and Kai Zhang "High-Speed Low-Power ViterbiDecoder Design for TCM Decoders"IEEE Transactions on very large scale integration (VLSI) systems, vol. 20,no. 4,april 2012.
- J. Jin and C. -Y. Tsui, "Low-power limited-search parallel state viterbi decoder implementation based onscarece state transition," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 15, no. 11, pp. 1172–1176,Oct. 2007.
- M. Boo, F. Arguello, J. D. Bruguera, R. Doallo, and E. L. Zapata. , ?High-performance VLSI architecture for the Viterbi algorithm,? IEEE Trans. on communications, vol. 45, no. 2, pp. 168–176, 1997.
- P. J. Black and T. H. Meng, ?A 1-Gb/s, four-state, sliding block Viterbi decoder,? IEEE Journal of Solid-State Circuits, vol. 32 no. 6, pp. 797–805, 1997.
- R. A. Abdallah and N. R. Shanbhag, "Error-resilient low-power viterbi decoder architectures,"IEEE Trans. Signal Process. , vol. 57, no. 12,pp. 4906–4917, Dec. 2009.
- Russell Henning ,and ChaitaliChakrabarti"An Approach for Adaptively Approximating theViterbi Algorithm to Reduce Power ConsumptionWhile Decoding Convolutional Codes" IEEE Trans. On Signal Processing, Vol. 52, No. 5, May 2004
- V. Tomas, ?Decoding of convolutional codes over the erasure channel,? IEEE Trans. on Information Theory, vol. 58,no. 1, pp. 90-108, Jan. 2012.
Index Terms
Keywords