CFP last date
20 January 2025
Call for Paper
February Edition
IJCA solicits high quality original research papers for the upcoming February edition of the journal. The last date of research paper submission is 20 January 2025

Submit your paper
Know more
The week's pick
Responsive image
HYBRID ANN AND FIREWORKS ALGORITHM FOR REAL-TIME SOFTWARE RELIABILITY PREDICTION

Ivy Botchway Felix Larbi Aryeh Boniface Kayode Alese
Random Articles
Reseach Article

Design of High-Speed Low-Power Two Level Voltage Converters using Multi-VTH CMOS Technology

by T. Sheela, T. Muthumanickam, A. Nagappan
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 84 - Number 14
Year of Publication: 2013
Authors: T. Sheela, T. Muthumanickam, A. Nagappan
10.5120/14648-2983

T. Sheela, T. Muthumanickam, A. Nagappan . Design of High-Speed Low-Power Two Level Voltage Converters using Multi-VTH CMOS Technology. International Journal of Computer Applications. 84, 14 ( December 2013), 49-52. DOI=10.5120/14648-2983

@article{ 10.5120/14648-2983,
author = { T. Sheela, T. Muthumanickam, A. Nagappan },
title = { Design of High-Speed Low-Power Two Level Voltage Converters using Multi-VTH CMOS Technology },
journal = { International Journal of Computer Applications },
issue_date = { December 2013 },
volume = { 84 },
number = { 14 },
month = { December },
year = { 2013 },
issn = { 0975-8887 },
pages = { 49-52 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume84/number14/14648-2983/ },
doi = { 10.5120/14648-2983 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:00:57.438003+05:30
%A T. Sheela
%A T. Muthumanickam
%A A. Nagappan
%T Design of High-Speed Low-Power Two Level Voltage Converters using Multi-VTH CMOS Technology
%J International Journal of Computer Applications
%@ 0975-8887
%V 84
%N 14
%P 49-52
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The paper primarily focuses on reducing the power consumption without diminishing the speed of the circuit by using multiple supply voltages (Multi-VDD). Two multi threshold (Multi-VTH) level converter circuits are proposed and it is compared with the conventional circuits for operating at different supply voltages (Multi-VDD). The converter circuits are individually optimized for minimum power consumption and propagation delay. The speed and power consumption for the proposed level converters were analyzed.

References
  1. F. Ishihara, F. Sheikh, and B. Nikolic "Level conversion for dual-supply systems" IEEE Trans. Very Large Scale Integration. (VLSI) Syst. , vol. 12, PP. 185-195, Feb. 2004.
  2. F. Ishihara, F. Sheikh, and B. Nikolic "Level conversion for dual-supply systems,"in Proc. Int. Symp. Low-Power Electronics Design, PP. 164–167, Aug. 2003.
  3. Jan M. Rabaey Anantha Chanderakasan Borivoje Nicolic "Digital Integrated Circuits" PHI Learning Limited New Delhi: 2008
  4. Jongyoon Jung; Taewhan Kim, "Statistical Viability Analysis for Detecting False Paths Under Delay Variation," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol. 32, no. 1, pp. 111,123, Jan. 2013
  5. S. H. Kulkarni, A. N. Srivastava, and D. Sylvester "A new algorithm for improved VDD Assignment in low power dual VDD systems" IEEE Trans. PP. 200-205, Aug. 2004.
  6. S. H. Kulkarni and D. Sylvester "High performance level conversion for dual VDD Design" IEEE Trans. Very Large Scale Integration. (VLSI) Syst. , vol. 12, no. 9, PP. 926-936, Sep. 2004.
  7. V. Kursun, R. M. Secareanu, and E. G. Firedman, "CMOS voltage interface circuit for Low power systems" IEEE Trans. Circuit System, Vol. 3, PP. 667-670, May 2002.
  8. V. Kursun and E. G. Friedman "Multi-Voltage CMOS Circuit Design" New York: Wiely 2006.
  9. M. Mohab Anis and M. Mohamed Elmarsy "Multi-Threshold CMOS digital circuits" University of Waterloo: Springer 2010.
  10. Neil H. E. Weste and Kamran Eshraghian "Principles of CMOS VLSI Design" University of Adelaide: Pearson Education: 2004.
  11. D. Nguyen, A. Davare, M. Orshansky, D. Chinnery, B. Thompson, and K. Keutzer "Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization" in Proc. Int. Symp. Low-Power Electronics Design, PP. 158–163, Sep. 2003.
  12. Sheriff A. Tawfik and Volkan Kursun , "Low power and high speed Multi threshold voltage Interface Circuit" IEEE Trans ,VLSI Systems. , VOL. 17 NO 5, MAY,2009
  13. A. Srivastava and D. Sylvester "Minimizing total power by simultaneous Vdd/Vth Assignment" in proc. IEEE Des. Autom. Conf. , PP. 400-403, Jan. 2003.
  14. Q . Wang and S. Vrudhula "Algorithms for minimizing standby power in deep submicron dual–Vt CMOS circuits " IEEE Trans. Computer- Aided Design, Vol. 21, PP. 306–318, Mar. , 2002.
Index Terms

Computer Science
Information Sciences

Keywords

CMOS Delay Threshold VDD Voltage level converters Multi-VTH

Powered by PhDFocusTM