Due to high complexity of VLSI systems used in various applications power dissipation becomes a limiting factor in VLSI circuits and systems, which arises from its switching activity influenced by the supply voltage and effective capacitance. Charging and discharging of the node capacitances in CMOS circuits creates power dissipation called as dynamic power dissipation . Thus to reduce dynamic power dissipation an adiabatic switching techniques is used in which the signal energies stored on circuit capacitances may be recycled instead of dissipated as heat. This can reduce the power dissipation but requires more number of transistors. Adiabatic logic offers a way to reuse the energy stored in the load capacitors rather than the traditional way of discharging the load capacitors to the ground and wasting this energy. Power dissipation is achieved by recovering the energy in the recover phase of the supply clock. Here a four bit digital multiplier is designed through the charge recovery logic and positive feedback adiabatic switching techniques are used for the design of above logic. Here all the gates , half adder , full adder are design using adiabatic switching techniques.

Adiabatic logic Microwind Multiplication Energy Recovery Power Supply