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Hardware Implementation of High Speed RC4 Algorithm in FPGA
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 83 - Number 4 |
| Year of Publication: 2013 |
| Authors: Chandra Mouli. R, K. R. K. Sastry |
10.5120/14437-2589
|
Chandra Mouli. R, K. R. K. Sastry . Hardware Implementation of High Speed RC4 Algorithm in FPGA. International Journal of Computer Applications. 83, 4 ( December 2013), 21-22. DOI=10.5120/14437-2589
Abstract
This paper presents high speed and an area efficient hardware implementation of the RC4 algorithm. The proposed design uses Block RAM (BRAM) implementation to reduce the area and to increase the speed of operation hence throughput. The proposed design uses only one 256 bytes simple dual port RAM for key stream generation and it takes 3 clock cycles per byte. It supports a variable key length of from 1 byte to 256 bytes and achieves 54. 8MB/s throughput at 164. 6MHz operating frequency. The design is targeted on XC2V250FG256 Xilinx FPGA and met the operating frequency of 164. 6MHz. The RC4 algorithm is implemented in Verilog HDL.
References
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