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Design and Implementation of an Efficient Instruction Set for Ternary Processor

by Satish Narkhede, Gajanan Kharate, Bharat Chaudhari
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 83 - Number 16
Year of Publication: 2013
Authors: Satish Narkhede, Gajanan Kharate, Bharat Chaudhari
10.5120/14536-2980

Satish Narkhede, Gajanan Kharate, Bharat Chaudhari . Design and Implementation of an Efficient Instruction Set for Ternary Processor. International Journal of Computer Applications. 83, 16 ( December 2013), 33-39. DOI=10.5120/14536-2980

@article{ 10.5120/14536-2980,
author = { Satish Narkhede, Gajanan Kharate, Bharat Chaudhari },
title = { Design and Implementation of an Efficient Instruction Set for Ternary Processor },
journal = { International Journal of Computer Applications },
issue_date = { December 2013 },
volume = { 83 },
number = { 16 },
month = { December },
year = { 2013 },
issn = { 0975-8887 },
pages = { 33-39 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume83/number16/14536-2980/ },
doi = { 10.5120/14536-2980 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:59:36.747640+05:30
%A Satish Narkhede
%A Gajanan Kharate
%A Bharat Chaudhari
%T Design and Implementation of an Efficient Instruction Set for Ternary Processor
%J International Journal of Computer Applications
%@ 0975-8887
%V 83
%N 16
%P 33-39
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Multi Valued Logic [MVL] is emerging as a promising choice for future computing technology. MVL has seen major advancement in the recent past due to several advantages offered by them over the binary logic, thus making it a thrust area for further research. The instruction set of the processor is its inherent entity. This paper presents design and implementation of an efficient instruction set for a ternary processor using Very-High-Speed Integrated Circuits, VHSIC Hardware Description Language [VHDL]. Twenty one instructions including various addressing modes such as register, direct and immediate mode are designed and implemented for 4-trit ternary processor. The required control signals are appropriately identified in the proposed design and enable the smooth operation of instructions. The designed 4 – trit instruction set signifies encouraging results that will pave the path for further developments in ternary processors.

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Index Terms

Computer Science
Information Sciences

Keywords

Multi Valued Logic Ternary logic VHDL.

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