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Reseach Article
Effect of Supply Voltage on Ability and Stability in IP3 SRAM Bit-Cell at 45nm CMOS Technology using N-Curve
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 83 - Number 16 |
| Year of Publication: 2013 |
| Authors: Toshiyanka Goswami, Jyoti Yadav, Shilpi Birla, Neeraj Kr. Shukla |
10.5120/14532-2929
|
Toshiyanka Goswami, Jyoti Yadav, Shilpi Birla, Neeraj Kr. Shukla . Effect of Supply Voltage on Ability and Stability in IP3 SRAM Bit-Cell at 45nm CMOS Technology using N-Curve. International Journal of Computer Applications. 83, 16 ( December 2013), 16-17. DOI=10.5120/14532-2929
Abstract
The Leakage power, performance, data retentation, and stability are the key challenges in Static Random Access Memory (SRAM) at Deep-Sub-Micron (DSM) CMOS technology. In the DSM technology, when threshold voltage, channel length, and gate oxide thickness are reduced, leakage currents in deep sub-micrometer regimes causes power dissipation in CMOS digital circuits which may affect the data ability and stability in the SRAM. In this work the effect of supply voltage has been observed in the IP3 SRAM Bit-Cell using N-Curve methodology at the room temperature (RT). To see the effect of supply voltage variations on the stability and ability parameters in the 6T and IP3 SRAM Bit-Cells, the supply voltage has been varied from 0. 6V to 1. 0V in step of 0. 1V. It has been seen that the read, write stability and ability are comparable in both cells at RT. The other design parameters taken from the CMOS technology available on 45nm are as tOX = 2. 4 nm, Vthn = 0. 224 V, and Vthp = 0. 24 V at RT = 27°C.
References
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