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Noise Sensitivity Analysis of 5 Stages Voltage Controlled Ring Oscillator at nm Technology

by Sheetal Soni, Shyam Akashe
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 83 - Number 15
Year of Publication: 2013
Authors: Sheetal Soni, Shyam Akashe
10.5120/14526-2922

Sheetal Soni, Shyam Akashe . Noise Sensitivity Analysis of 5 Stages Voltage Controlled Ring Oscillator at nm Technology. International Journal of Computer Applications. 83, 15 ( December 2013), 31-35. DOI=10.5120/14526-2922

@article{ 10.5120/14526-2922,
author = { Sheetal Soni, Shyam Akashe },
title = { Noise Sensitivity Analysis of 5 Stages Voltage Controlled Ring Oscillator at nm Technology },
journal = { International Journal of Computer Applications },
issue_date = { December 2013 },
volume = { 83 },
number = { 15 },
month = { December },
year = { 2013 },
issn = { 0975-8887 },
pages = { 31-35 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume83/number15/14526-2922/ },
doi = { 10.5120/14526-2922 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:59:28.645414+05:30
%A Sheetal Soni
%A Shyam Akashe
%T Noise Sensitivity Analysis of 5 Stages Voltage Controlled Ring Oscillator at nm Technology
%J International Journal of Computer Applications
%@ 0975-8887
%V 83
%N 15
%P 31-35
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In present paper, design of differential ring oscillator using replica bias circuit has been presented. Qualitative analysis of jitter and phase noise of differential ring oscillators in the time and frequency domain is presented respectively which shows great results for the design issues of voltage controlled ring oscillator. The effect of the different number of transistors and their symmetrical arrangement to phase noise and jitter is analyzed. Good agreement between qualitative and quantitative measurements is observed using the cadence virtuoso tool, which is exceedingly applicable in ultra high speed Wi-Fi communications.

References
  1. Design of low-voltage wide tuning range cmos multipass voltage-controlled ring oscillator by jie ren, Dalhousie University Halifax, Nova Scotia march 2011.
  2. S. Y. Lee and J. Y. Hsieh, "Analysis and implementation of a 0. 9Vvoltage-controlled oscillator with low phase noise and low powerdissipation," IEEE Transaction on Circuits and Systems II, vol. 55,no. 7, pp. 624-627, Jul. 2008.
  3. B. Catli and M. M. Haskell, "A 0. 5V 3. 6/5. 2 GHz CMOS multi-bandVCO for ultra low-voltage wireless applications," IEEE InternationalSymposium on Circuits and Systems, May 2008, pp. 996-999.
  4. C. K. K. YANG, R. FARJAD-RAD, M. A. HOROWITZ, A 0. 5- m CMOS 4. 0-Gbit/s serial link transceiver with data recovery using oversampling, IEEE J. Solid-State Circuits, vol. 33, (1998), 713-722.
  5. L. S. Paula, S. Banpi, E. Fabris, and A. A. Susin, "A wide band CMOS differential voltage-controlled ring oscillators," InternationalIEEE Northeast Workshop on Circuits and System Design, Jun. 2008,pp. 9-12. 2008.
  6. T. Cao, D. T. Wisland, T. S. Lande, and F. Moradi, "Low-voltage, low-power, and wide-tuning range VCOfor frequency ?? modulator," IEEE Conference NORCHIP, Nov. pp. 79-84. 2008.
  7. H. R. Kim, C. Y. Cha, S. Min Oh, M. S. Yang, and S. G. Lee, "A very low-power quadrature VCO with back-gate coupling," IEEE Journalof Solid-State Circuits, vol. 39, no. 6, Jun. 2004.
  8. M. J. Deen, M. H. Kazemeini, and S. Naseh, "Performancecharacteristics of an ultra-low power VCO," International Symposiumon Circuits and Systems, May 2003, pp. 697-700. 2003.
  9. K. Roy and S. C. Prasad, "Low power CMOS circuit design," WielyPvt Ltd, India, Feb. 2002, pp. 214-219.
  10. B. Bero, J. Nyathi, "Bulk CMOS device optimization for high-speedand ultra-low power operations," IEEE International MidwestSymposium on Circuits and Systems, vol. 2, Aug. 2006, pp. 221 – 225.
  11. S. Docking, M. Sachdev, A Method to Derive an Equation for the Oscillation Frequency of a Ring Oscillator, IEEE Trans. on Circuits and Systems - I: Fundamental Theory and Applications, vol. 50, 2,(2003), 259-264.
  12. A. Hajimiri, S. Limotyrakis, and T. H. Lee, "Jitter and phase noise inring oscillators," IEEE Journal of Solid-State Circuits, vol. 34, no. 6,pp. 790-804, Jun. 1999.
  13. Docking S and Sachdev M. IEEE J Solid State Circuit, 39 (2004) 533.
  14. Alioto M. and Palumbo G, IEEE Trans or Circuits and Syst I, 48 (2001) 210.
  15. Sanyal A. Rastogi, A. Wei Chen Kundu, S. Computers, IEEE Transactions on July 2010, 59.
  16. Design of ring oscillator based VCO" written by George Lee, Professor Leung March 29, 2005
  17. C. H. PARK, O. KIM, B. KIM, A 1. 8-GHz self-calibrated phase locked loop with precise I/Q matching, IEEE J. Solid-State Circuits, vol. 36, (2001), 777-783.
  18. B. RAZAVI, A 2-GHz 1. 6-mW phase-locked loop, IEEE J. Solid-State Circuits, vol. 32,(1997), 730-735.
  19. G. JOVANOVI´C, M. STOJ?CEV, A Method for Improvement Stability of a CMOS Voltage Controlled Ring Oscillators, ICEST 2007, Proceedings of Papers, vol. 2, pp. 715-718, Ohrid, Jun 2007.
  20. TODD CHARLES WEIGANDT, Low-Phase-Noise, Low-Timing-Jitter Design Techniques for Delay Cell Based VCOs and Frequency Synthesizers, PhD dissertation, University of California, Berkeley, 1998
Index Terms

Computer Science
Information Sciences

Keywords

Ring oscillator Replica bias Phase noise and Jitter.

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