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Analysis and Implementation of Modified Feedthrough Logic for High Speed and Low Power Structures
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 82 - Number 18 |
| Year of Publication: 2013 |
| Authors: M. Lakshmi, K. Nareshkumar, Sagara Pandu |
10.5120/14266-2412
|
M. Lakshmi, K. Nareshkumar, Sagara Pandu . Analysis and Implementation of Modified Feedthrough Logic for High Speed and Low Power Structures. International Journal of Computer Applications. 82, 18 ( November 2013), 29-31. DOI=10.5120/14266-2412
Abstract
In this paper, the design of a low power and high performance dynamic circuit using a new CMOS domino logic family called feedthrough logic is presented. The need for faster circuits with low power dissipation has made it common practice to use feedthrough logic. The proposed circuit for low power improves dynamic power consumption as compared to the existing feedthrough logic and improves its speed. The proposed circuit is simulated using 90nm with power supply 0. 9 V CMOS process technology from Cadence(R) Virtuoso(R). Exhaustive simulation results in Cadence environment be evidence for that the proposed modified FTL structure has an advantage in reduction of the dynamic power approximately by 55% and accomplish a speed up to 45% on 8-bit ripple carry adder in contrast to existing feedthrough logic.
References
- S. M. Kang, Y. Leblebici, CMOS Digital Integrated Circuits: Analysis & Design, TATA McGraw- Hill Publication, 3e, 2003.
- J. M. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits: A Design perspective 2e Prentice-Hall, Upper saddle River, NJ, 2002.
- R. K. Krishnamurthy, S. Hsu, M. Anders, B. Bloechel, B. Chatterjee, M. Sachdev, S. Borkar, "Dual Supply voltage clocking for 5GHz 130nm integer execution core," proceedings of IEEE VLSI Circuits Symposium, Honolulu, pp. 128-129, June 2002.
- S. vangal, Y. Hoskote, D. Somasekhar, V. Erraguntla, J. Howard, G. Ruhl,V. Veeramachaneni, D. Finan, S. Mathew, and N. Borkar, "A 5-GHz floating point multiply-accumulator in 90-nm dual VT CMOS," in Proc. IEEE Int. Solid-State Circuits Conf. , San Francisco, CA, pp. 334–335, Feb. 2003.
- V. Navarro-Botello, J. A. Montiel-Nelson, and S. Nooshabadi, "Analysis of high performance fast feedthrough logic families in CMOS," IEEE Trans. Cir. & syst. II, vol. 54, no. 6, pp. 489-493,Jun. 2007.
- J. L. Rossello, C. de Benito, and J. Segura, "A compact gate-level energy and delay model of dynamic CMOS gates," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 10, pp. 685–689, Oct. 2005.
- S. Nooshabadi and J. A. Montiel-Nelson, "Fast feedthrough logic: A high-performance logic family for GaAs," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 11, pp. 2189–2203, Nov. 2004.
- K. Navi, V. Foroutan, M. Rahimi Azghadi, M. Maeen, M. Ebrahimpour, M. Kaveh, O. Kavehei, "A Novel low power full-adder cell with new technique in designing logical gates based on static CMOS Inverter," ELSEVIER Microelectronics Journal, Vol. 40, (2009), 1441–1448.
- V. Navarro-Botello, J. A. Montiel-Nelson, and S. Nooshabadi, "Low power arithmetic circuits in feedthrough dynamic CMOS logic," in Proc. 49th IEEE Int. Midwest Symp. Circuits, Syst. (MWSCAS'06), San Juan, Puerto Rico, August 2006.
- V. Navarro-Botello, J. A. Montiel-Nelson, and S. Nooshabadi, "Fast Adder Design in Dynamic Logic" in IEEE Trans. Circuits Syst. 2007.
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