The week's pick
Random Articles
Reseach Article
Implementation of Low Leakage and High Performance 8-Bit ALU for Low Power Digital Circuits
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 82 - Number 18 |
| Year of Publication: 2013 |
| Authors: Sk. Mahammad Akram, V. Leela Rani, K. Sailaja |
10.5120/14265-2411
|
Sk. Mahammad Akram, V. Leela Rani, K. Sailaja . Implementation of Low Leakage and High Performance 8-Bit ALU for Low Power Digital Circuits. International Journal of Computer Applications. 82, 18 ( November 2013), 24-28. DOI=10.5120/14265-2411
Abstract
The insist for portable devices is fulfilled by the growing CMOS technology. As the size of the transistor shrinks, the leakage power component augments exponentially. Thus it becomes a critical metric for the future technologies. This paper deals with the techniques like GATED VDD, AVLS, AVLG, and AVL for reducing leakage power. These techniques are implemented on 8-bit ALU. 80% of cutback in leakage power can be achieved by applying proposed technique with minimum delay and area overhead. The circuit is simulated on cadence(R) Virtuoso(R) in 90 nanometer CMOS technology.
References
- V. Leela Rani, M. Madhavi Latha, A. Sai Ramesh "GALEORSTACK-a novel leakage reduction technique for low power VLSI design "in proc. of International Journal of Computer Applications, volume48-NO. 8,JUNE 2012.
- Urvashi Chaudhari, Rachna Jani "A Study of Circuit Level Leakage Reduction Techniques in Cache Memories" International Journal of Engineering Research and Applications (IJERA), pp. 457-460, March -April 2013.
- Shyam Akashe, Gunakesh Sharma, Vinod Rajak, Richa Pandey "Implementation of high performance and low leakage half subtractor circuit using AVL technique" IEEE 978-1-4673-4805-8/12/2012
- Michael Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, and T. N. Vijaykumar "A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories". ISLPED '00, Rapallo, Italy. Copyright 2000 ACM 1-581 13-190-9/00/0007
- V. De and S. Borkar, "Technology and design challenges for low power and high performance," in Proc. Int. Symp. Low Power Electronics and Design, pp. 163–168,1999.
- Kaushik Roy, Saibal Mukhopadhyay and Hamid Mahmoodi-Meimand, "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Sub micrometer CMOS Circuits," proceedings of the IEEE, vol. 91, no. 2, pp305-327, February 2003
- Farzan Fallah, Massoud Pedram "Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits" in IEICE Transactions, pp. 509-519, 2005.
- Milind Gautam and Shyam Akashe, "Reduction of Leakage Current and Power in Full Subtractor Using MTCMOS Technique" 2013 International Conference on Computer Communication and Informatics (ICCCI -2013), Jan. 04 – 06, 2013.
Index Terms
Keywords