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Analysis of Leakage Power Reduction Techniques for Low Power VLSI Design
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 82 - Number 18 |
| Year of Publication: 2013 |
| Authors: K. Sailaja, V. Leela Rani, Sk. Mahammad Akram |
10.5120/14264-2408
|
K. Sailaja, V. Leela Rani, Sk. Mahammad Akram . Analysis of Leakage Power Reduction Techniques for Low Power VLSI Design. International Journal of Computer Applications. 82, 18 ( November 2013), 20-23. DOI=10.5120/14264-2408
Abstract
Power dissipation has become one of the major concerns of VLSI circuit design with the rapid launching of battery operated applications. In high performance designs, the leakage component of power consumption is comparable to the switching component. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. In this paper, an 8X8 multiplier is designed using different leakage power reduction techniques like MTCMOS, DUAL-Vt and LECTOR. All the above mentioned techniques are simulated using Cadence virtuoso tool in 90nm technology.
References
- Farzan Fallah, Massoud Pedram "Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits" IEICE Transactions, 2005, pp. 509-519.
- Kaushik Roy, Saibal Mukhopadhyay and Hamid Mahmoodi-Meimand, "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Sub micrometer CMOS Circuits," PROCEEDINGS OF THE IEEE, VOL. 91, NO. 2, FEBRUARY 2003.
- James T. Kao and Anantha P. Chandrakasan, "Dual-Threshold Voltage Techniques for Low-Power Digital Circuits," IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 7, JULY 2000.
- Shyam Akashe, Nitesh Kumar Tiwari, Jayram Shrivas and Rajeev Sharma, "A Novel High Speed & Power Efficient Half Adder Design Using MTCMOS Technique in 45 Nanometre Regime" IEEE International Conference on Advanced Communication Control and Computing Technologies (ICACCCT) 2012.
- Milind Gautam and Shyam Akashe, "Reduction of Leakage Current and Power in Full Subtractor Using MTCMOS Technique" 2013 International Conference on Computer Communication and Informatics (ICCCI -2013), Jan. 04 – 06, 2013.
- J. Jaffari and A. Afzali-Kusha, "New Dual-Threshold Voltage Assignment Technique for Low-Power Digital Circuits," 0-7803-8656-6/04/$20. 00, pp. 413-416 IEEE 2004.
- L. Wei. 2. Chen, K. Roy, M. C. Johnson, Y. Ye and V. De, "Design and optimization of dual threshold circuits for low voltage low power applications," IEEE Transactions on VLSI Systems. Vol. 7. No. 1, pp. 16-24. Mar. 1999.
- B. Dilip1, P. Surya Prasad2 & R. S. G. Bhavani3 "Leakage Power Reduction In CMOS Circuits Using Leakage Control Transistor Technique In Nanoscale Technology" International Journal of Electronics Signals and Systems (IJESS) ISSN: 2231- 5969, Vol-2 Issue-1, 2012.
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