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Area-Delay Estimation by Concurrent Optimization of FPGA Architecture Parameters using Geometric Programming

by Y. Pandurangaiah, J. Venkat Reddy, G. Kalyan Chakravarthy
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 82 - Number 18
Year of Publication: 2013
Authors: Y. Pandurangaiah, J. Venkat Reddy, G. Kalyan Chakravarthy
10.5120/14261-2088

Y. Pandurangaiah, J. Venkat Reddy, G. Kalyan Chakravarthy . Area-Delay Estimation by Concurrent Optimization of FPGA Architecture Parameters using Geometric Programming. International Journal of Computer Applications. 82, 18 ( November 2013), 4-11. DOI=10.5120/14261-2088

@article{ 10.5120/14261-2088,
author = { Y. Pandurangaiah, J. Venkat Reddy, G. Kalyan Chakravarthy },
title = { Area-Delay Estimation by Concurrent Optimization of FPGA Architecture Parameters using Geometric Programming },
journal = { International Journal of Computer Applications },
issue_date = { November 2013 },
volume = { 82 },
number = { 18 },
month = { November },
year = { 2013 },
issn = { 0975-8887 },
pages = { 4-11 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume82/number18/14261-2088/ },
doi = { 10.5120/14261-2088 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:58:03.610241+05:30
%A Y. Pandurangaiah
%A J. Venkat Reddy
%A G. Kalyan Chakravarthy
%T Area-Delay Estimation by Concurrent Optimization of FPGA Architecture Parameters using Geometric Programming
%J International Journal of Computer Applications
%@ 0975-8887
%V 82
%N 18
%P 4-11
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper presents the application of geometric programming for combined high-level and low-level architecture parameter exploration. This paper builds an geometric programming framework for reconfigurable architectures, and presents a full delay and area model of an FPGA. This optimization allows high-level architectural parameter selection and the transistor sizing to be done concurrently. The transistor values are derived using 45nm predictive technology model. CVX framework for MATLAB is used to run the geometric programming framework. The area and critical path delay are determined for given cost function by single-stage and multi-stage approach.

References
  1. A. M. Smith, G. A. Constantinides, and P. Y. K. Cheung, "Area estimation and optimization of FPGA routing fabrics," in Int'l Conf. on Field-Programmable Logic and Applications, Sep. 2009.
  2. W. Fang and J. Rose, "Modeling FPGA routing demand in early-stage architecture development," in Int'l Symp. on Field-Programmable Gate Arrays, Feb. 2008, pp. 139–148.
  3. J. Luu, I. Kuon, P. Jamieson, T. Campbell, A. Ye, M. Fang, and J. Rose, "Vpr 5. 0: FPGA CAD and architecture exploration tools with singledriver routing, heterogeneity and process scaling," in Int'l Symp. on Field-Programmable Gate Arrays, Feb. 2009, pp. 133–142.
  4. A. Lam, S. J. Wilton, P. Leong, and W. Luk, "An analytical model describing the relationships between logic architecture and FPGA density," in Int'l Conf. on Field-Programmable Logic and Applications, Sep. 2008.
  5. V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep- submicron FPGAs. Kluwer Academic Publishers, 1999.
  6. S. P. Boyd, S. -J. Kim, D. D. Patil, and M. A. Horowitz, "Digital circuit optimization via geometric programming," Operations Research, vol. 53, no. 6, pp. 899–932, Nov-Dec 2008.
  7. I. Kuon and J. Rose, "Area and delay trade-offs in the circuit and architecture design of FPGAs," in Int'l Symp. on Field-Programmable Gate Arrays, Feb. 2008, pp. 149–158.
  8. M. Lin, A. E. Gamal, Y. -C. Lu, and S. Wong, "Performance benefits of monolithically stacked 3-D FPGA," IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. 26, no. 2, pp. 216–229, Feb. 2007.
  9. A. M. Smith, J. Das, and S. J. E. Wilton, "Wirelength modeling for homogeneous and heterogeneous FPGA architectural development," in Int'l Symp. on Field-Programmable Gate Arrays, Feb. 2009, pp. 181– 190.
  10. J. Das, S. J. Wilton, P. Leong, and W. Luk, "An analytical model describing the relationships between logic architecture and FPGA density," in Int'l Conf. on Field-Programmable Logic and Applications, Sep. 2009.
  11. M. Grant and S. Boyd, "CVX: Matlab software for disciplined convex programming (web page and software)," Feb. 2009, http://stanford. edu/ ?boyd/cvx.
  12. S. Joshi and S. Boyd, "An efficient method for large-scale gate sizing," IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 55, no. 9, pp. 2760–2773, Oct. 2008.
  13. W. C. Elmore, "The transient analysis of damped linear networks with particular regard to wideband amplifiers," J. Appl. Phys. , vol. 19, no. 1, pp. 55–63, Jan. 1948.
  14. W. Zhao and Y. Cao, "New generation of predictive technology model for sub-45nm design exploration," in Int'l Symposium on Quality Electronic Design, 2006. ISQED '06. , March 2006, pp. 6 pp. –590.
  15. S. -J. Kim, S. P. Boyd, S. Yun, D. D. Patil, and M. A. Horowitz, "A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing," Optim Eng, vol. 8, no. 4, pp. 397– 430, 2007.
Index Terms

Computer Science
Information Sciences

Keywords

Geometric Programming Reconfigurable architectures

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