The week's pick
Reseach Article
Area Efficient 1-Bit Comparator Design by using Hybridized Full Adder Module based on PTL and GDI Logic
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 82 - Number 10 |
| Year of Publication: 2013 |
| Authors: Anjali Sharma, Richa Singh, Pankaj Kajla |
10.5120/14150-2316
|
Anjali Sharma, Richa Singh, Pankaj Kajla . Area Efficient 1-Bit Comparator Design by using Hybridized Full Adder Module based on PTL and GDI Logic. International Journal of Computer Applications. 82, 10 ( November 2013), 5-13. DOI=10.5120/14150-2316
Abstract
In this paper an area efficient 17T 1-bit hybrid comparator design has been presented by hybridizing PTL and GDI techniques. The proposed 1-bit comparator design consist of 9 NMOS and 8 PMOS. A PTL and GDI full adder module has been used which consume less area at 120 nm as compared with the previous full adder designs. The proposed Hybrid 1-bit comparator design is based on this area efficient 9T full adder module. To improve area and power efficiency a cascade implementation of XOR module has been avoided in the used full adder module. Full adder modules outputs have been used for the generation of three different output of 1-bit comparator designs. The proposed 1-bit comparator has been designed and simulated using DSCH 3. 1 and Microwind 3. 1 on 120nm. Also the simulation of layout and parametric analysis has been done for the proposed 1-bit comparator design. Power and current variation with respect to the supply voltage has been performed on BSIM-4 and LEVEL-3 on 120nm. Results show that area consumed by the proposed hybrid adder is 329. 3µm2 on 120nm technology. At 1. 4V input supply voltage the proposed 1-bit hybrid comparator consume 0. 367mW power at BSIM-4 and 0. 411mW power at LEVEL-3 and 2. 313mA current at BSIM-4 and 3. 047mA current at LEVEL-3 model
References
- N. Weste and K. Eshraghian, (2002) Principles of CMOS VLSI Design: A System Perspective Reading, Pearson Education, Addison–Wesley.
- Sung-Mo Kang, Yusuf Leblebici, (2003) CMOS Digital Integrated Circuits: Analysis and Design, TATA Mc GRAW-HILL.
- Etienne Sicard, Sonia Delmas Bendhia, Basic of CMOS Cell Design, TATA Mc GRAW-HILL.
- Etienne Sicard, Sonia Delmas Bendhia, Advance of CMOS Cell Design, TATA Mc GRAW-HILL.
- Anjuli, Satyajit Anand, "2-Bit Magnitude Comparator Design Using Different Logic Styles," International Journal of Engineering Science Invention, Vol. 2, No. 1, pp. 13-24.
- A. N. Nagamani, H V Jayashree , H R Bhagyalakshmi, "Novel Low Power Comparator Design using Reversible Logic Gates," International Journal of Computer Science and Engineering,Vol. 2, No. 4, pp. 566-574.
- H V Jayashree, A. N. Nagamani, H R Bhagyalakshmi, "Modified TOFFOLI GATE and its Applications in Designing Components of Reversible Arithmetic and Logic Unit," international journal of Advance Research in Computer Science and Software Engineering, Vol. 2, No. 7, pp. 207-210.
- H G Rangaraju, Vinayak Hegde, K B Raja, "Design and Optimization of n-bit Reversible Binary Comparator," International Journal of Computer Applications, Vol. 55, No. 18, pp. 22-30.
- Anjuli, Satyajit Anand, "High speed 64-Bit CMOS Binary Comparator," International Journal of Innovative Systems Design and Engineering, Vol. 4, No. 2, pp. 45-58.
- Geetanjali Sharma, Uma Nirmal, Yogesh Misra, "A Low Power 8-bit Magnitude Comparator with Small Transistor Count using Hybrid PTL/CMOS Logic," International Journal of Computational Engineering & Management, Vol. 12, No. 2, pp. 110-115.
- Anjali Sharma, Richa Singh, Rajesh Mehra, Member, IEEE, "Low Power TG Full Adder Design Using CMOS Nano Technology," IEEE International Conference on Parallel, Distributed and Grid Computing, pp. 210-213.
- Anjali Sharma, Rajesh Mehra, "Area and Power Efficient CMOS Adder Design by Hybridizing PTL and GDI Technique," International Journal of Computer Applications, Vol. 66, No. 4, pp. 15-22.
- Chiou-Kou Tung; Yu-Cherng Hung; Shao-Hui Shieh; Guo-Shing Huang," A Low -Power High-speed Hybrid CMOS Full Adder For Embedded System," IEEE transactions on Design and Diagnostics of Electronic Circuits and Systems, vol. 13, No. 6, pp. -1 – 4, 2007.
- Subodh Wairya, Rajendra Kumar Nagaria and Sudarshan Tiwari, "New Design Methodologies for High Speed Mixed Mode Full Adder Circuits," International Journal of VLSI and Communication Systems, Vol. 2, No. 2, pp. -78-98, 2011.
- Subodh Wairya, Rajendra Kumar Nagaria ,Sudarshan Tiwari, "Comparative Performance Analysis of XOR/XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design ", International Journal Of VLSI Design & Communication System, pp. -221-242, 2012.
- Morgenshtein, A. ; Fish, A. ; Wagner, I. A. , "Gate-diffusion input (GDI): A Power Efficient Method for Digital Combinational circuits," IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Vol. 10 , No. 5 ,pp. 566 - 581 , 2002.
- Morgenshtein, A. ; Fish, A. ; Wagner, A, "Gate-diffusion input (GDI)-A novel power efficient method for digital circuits: A Design Methodology," IEEE International Conference, pp. 39 – 43,2001
- Po-Ming Lee; Chia-Hao Hsu; Yun-Hsiun Hung, " Novel 10-T full adders realized by GDI structure" Components, Circuits, Devices &Systems ,Engineered Materials, Dielectrics & Plasmas ,pp. 115 - 118 , 2007.
- Shahid Jaman, Nahian Chawdhury, Aasim Ullah, Muhammad Foyazur Raham, " A New High Speed-Low Power 12 Transistor Full Adder Design With GDI Technique," international Journal of Science & Engineering Research," Vol. 3,No. 7,2012.
- Pakkiraiah Chakali, K Sreeknath Yadav, Dilli Babu S, " A Noval Low Power Binary to Gray Code Converter Using Gate Diffusion Input (GDI), IOSR journal of engineering ,vol. 2, No. 8, pp. 107-111,2012
- Microwind and DSCH version 3. 1, User's Manual, Copyright 1997-2007, Microwind INSA France
Index Terms
Keywords