This paper illustrates the system on chip (SoC) debugging and analyses its behavior at several test conditions by verifying the functional aspects of the on-chip bus. Here an Advanced High performance bus (AHB) is selected, since the AHB bus signals are difficult to observe as they are deeply embedded in the system on chip and these I/O pins to access these signals is not possible. Hence we embed a bus tracer in SoC to capture and compress the bus signals. The tracer is successfully verified in FPGA. In this manuscript the selected software is XILINX ISE software design environment for RTL synthesis and model-Sim simulation software to verify the timing diagrams of the AHB SoC modules designed. The FPGA used is SPARTAN 3E (XC3S500E).

On-chip bus AMBA SoC debugging COMPRESSION FPGA