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Design of High Speed Modulo 2n+1 Adder

by M. Varun, M. Nagarjuna, M. Vasavi
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 81 - Number 17
Year of Publication: 2013
Authors: M. Varun, M. Nagarjuna, M. Vasavi
10.5120/14213-2110

M. Varun, M. Nagarjuna, M. Vasavi . Design of High Speed Modulo 2n+1 Adder. International Journal of Computer Applications. 81, 17 ( November 2013), 5-11. DOI=10.5120/14213-2110

@article{ 10.5120/14213-2110,
author = { M. Varun, M. Nagarjuna, M. Vasavi },
title = { Design of High Speed Modulo 2n+1 Adder },
journal = { International Journal of Computer Applications },
issue_date = { November 2013 },
volume = { 81 },
number = { 17 },
month = { November },
year = { 2013 },
issn = { 0975-8887 },
pages = { 5-11 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume81/number17/14213-2110/ },
doi = { 10.5120/14213-2110 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:56:17.446619+05:30
%A M. Varun
%A M. Nagarjuna
%A M. Vasavi
%T Design of High Speed Modulo 2n+1 Adder
%J International Journal of Computer Applications
%@ 0975-8887
%V 81
%N 17
%P 5-11
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The two different architectures for adders are introduced in this paper. The first one is built around a sparse carry computation unit that computes only some of the carries of modulo 2n+1 addition. This sparse approach is enabled by the introduction of inverted circular idem potency property of the parallel-prefix carry operator and its regularity and area efficiency are further enhanced by the introduction of a new prefix operator. The resulting diminished-1 adder can be implemented in a smaller area and consume less power compared to all earlier proposals, maintaining a high operation speed. The second adder architecture unifies the design of modulo 2n+1 adder. Both the adders are derived and compared by using the simulation results.

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Index Terms

Computer Science
Information Sciences

Keywords

IEAC adder Sparse-4 adder RNS

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